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• Fan-Out Embedded Bridge Solution for Chiplet/HBM Integration
  crossref Mark Liao, Vito Lin, Andrew Kang, Long-Yuan Wang 等 2024-04-11T18:46:52Z 置信度 0.70
• A physics-constrained and data-driven approach for thermal field inversion in chiplet-based packaging
  crossref Yupeng Qi, Yue Wu, Jie Xiong, Shunbo Hu 等 2025-12-24T09:36:29Z 置信度 0.70
• Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
  crossref Hung Khac Le, Seonghyun Park, SoYoung Kim 2026-01-22T20:59:20Z 置信度 0.70
• Reverse Laser Assisted Bonding (R-LAB) Technology for Chiplet Module Bonding on Substrate
  crossref SeokHo Na, MinHo Gim, GaHyeon Kim, DongSu Ryu 等 2023-01-18T18:54:40Z 置信度 0.70
• Chiplet-based Architecture Design for Multi-Core Neuromorphic Processor
  crossref Jingjing Lan, Vishnu P. Nambiar, Rheeshaalaen Sabapathy, Mihai Dragos Rotaru 等 2022-01-05T20:42:25Z 置信度 0.70
• Research on Double-Layer Networks-on-Chip for Inter-Chiplet Data Switching on Active Interposers
  crossref Xiaolong Duan, Min Miao, Zhuanzhuan Zhang, Liang Sun 2021-10-26T21:09:36Z 置信度 0.70
• Thermal Management Verification Platform for Chiplet Functional Unit
  crossref Yuxin Ye, Guoran Lu, Peijie Li, Yanbin Hu 等 2026-02-24T20:55:10Z 置信度 0.70
• Power Envelope Analysis for the Thermal Optimization of a Chiplet Module
  Abstract In this paper, the thermal performances of a Chiplet module with different numbers of dies were studied. The Chiplet module was assumed to be placed in the same server system, with the same ambient condition, and using the same heat sink. A thermal si…
  crossref Eric Ouyang, Xiao Gu, Yonghyuk Jeong, Michael Liu 2022-12-07T16:30:36Z 置信度 0.70
• Board level underfill solution for Chiplet Design and Heterogeneous Integration package
  crossref Qingxu Yang, Xiaolong Hu, Jing Lu, Qian Zhang 等 2024-04-11T18:46:52Z 置信度 0.70
• Power Electronics Packaging
  crossref 2015-05-18T21:11:37Z 置信度 0.70
• Study of High-Speed Bonding Process with Thin Adhesive for Chiplet Heterogenous Integration
  crossref T. Kudo, Y. Satake, T. Funaki, N. Araki 等 2023-05-23T17:47:38Z 置信度 0.70
• Metal-Embedded Chiplet Assembly for Microwave Integrated Circuits
  crossref Florian Herrault, Joel C. Wong, Dean Regan, David F. Brown 等 2020-07-28T22:23:23Z 置信度 0.70
• 3D Interconnect Inspection for Chiplet Packaging using White-light Scanning and Phase-Shifting Interferometry
  crossref Shahab Chitchian, SeYong Song, HyeJin Song, HyunMin Lee 等 2024-12-16T19:15:14Z 置信度 0.70
• Challenges and Prospects of Chiplet Package Design
  crossref 2024-12-31T22:10:49Z 置信度 0.70
• Indium Through Si Via for Quantum Chiplet Integration
  crossref Yugi Otake, Mai Thi Ngoc La, Kenta Hayama, Jowesh Avisheik Goundar 等 2025-05-21T17:36:38Z 置信度 0.70
• Warpage and Stress Analysis in Molded 2.5D Package Chiplet Integration
  crossref Meng-Chi Hsu, Hung-Chun Yang, Wei-Hong Lai, Chin-Li Kao 等 2025-01-02T19:17:35Z 置信度 0.70
• Multichip and ThreeDimensional Packaging
  crossref 2015-05-18T21:11:37Z 置信度 0.70
• Process Integration and Reliability Challenges of Through-Glass Vias for Glass-Based Advanced Packaging: A Focused Review.
  europepmc 2026 置信度 0.80
• Development and Optimization of Fine-Pitch RDL for RDL Interposer, and Embedded Bridge Die Interposer Fabrication Using Fan-Out Wafer-Level Packaging Technology
  europepmc 2026 置信度 0.80
• Study on Stress Distribution and Its Impact on Reliability of SiO<sub>2</sub>-Based Inorganic Chiplet Gap Filling.
  europepmc 2025 置信度 0.80
• Thermal Side-Channel Threats in Densely Integrated Microarchitectures: A Comprehensive Review for Cyber-Physical System Security.
  europepmc 2025 置信度 0.80
• A Comprehensive Experimental and Finite Element Analysis Study on the Bonding Strength Evaluation of Wafer-to-Wafer Hybrid Bonding with Polyimide Film Dielectrics.
  europepmc 2026 置信度 0.80
• Fabrication of High-Density Multimodal Neural Probes Based on Heterogeneously Integrated CMOS.
  europepmc 2026 置信度 0.80
• Interposer-Based ESD Protection: A Potential Solution for μ-Packaging Reliability of 3D Chips.
  europepmc 2025 置信度 0.80
• Electrothermal co-optimization of 2.5D power distribution network with TTSV cooling.
  europepmc 2025 置信度 0.80
• Integrated chips: An interdisciplinary evolution in the Post-Moore Era.
  europepmc 2024 置信度 0.80
• ChipletQuake: On-Die Digital Impedance Sensing for Chiplet and Interposer Verification.
  europepmc 2025 置信度 0.80
• A Review of Embedded Artificial Intelligence Research (2023-2026): Technological Advancements, Representative Advances, and Future Prospects.
  europepmc 2026 置信度 0.80
• A thermal resistance prediction model for heterogeneous integrated chips incorporating an AI-based BP neural network.
  europepmc 2026 置信度 0.80
• A Sharp Phase Transition Polymer for High Spatial Selectivity in Microtransfer Printing.
  europepmc 2025 置信度 0.80
• The Big Chip: Challenge, model and architecture.
  europepmc 2024 置信度 0.80
• Measurement and Analysis of Interconnects' Resonance and Signal/Power Integrity Degradation in Glass Packages.
  europepmc 2025 置信度 0.80
• An Embedded Trace Redistribution Layer with Rounded-Bottom Cu Geometry and Ti Capping for Enhanced Electromigration Reliability.
  europepmc 2026 置信度 0.80
• Thermal stability enhancement of low temperature Cu-Cu bonding using metal passivation technology for advanced electronic packaging.
  europepmc 2025 置信度 0.80
• Stitch-Less Lithography Empowered by Multi-Dimensional Holography.
  europepmc 2026 置信度 0.80
• Design Considerations of an Analog Voltage Mode Readout Circuit for the CMOS-SOI-MEMS Gas Sensor Dubbed GMOS.
  europepmc 2025 置信度 0.80
• Advanced Design for High-Performance and AI Chips.
  Recent years have witnessed transformative changes brought about by artificial intelligence (AI) techniques with billions of parameters for the realization of high accuracy, proposing high demand for the advanced and AI chip to solve these AI tasks efficiently…
  europepmc 2025 置信度 0.80
• Flexible electronic-photonic 3D integration from ultrathin polymer chiplets.
  europepmc 2024 置信度 0.80
• Perspective: an optoelectronic future for heterogeneous, dendritic computing.
  europepmc 2024 置信度 0.80
• A Study on Regulating the Residual Stress of Electroplated Cu by Manipulating the Nanotwin Directions.
  europepmc 2024 置信度 0.80
• Poly(ionic liquid)s: A Promising Matrix for Thermal Interface Materials.
  europepmc 2024 置信度 0.80
• SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.
  Lightweight Unmanned Aerial Vehicles (UAVs) have limited space, low payload capacity, and constrained power supply capabilities. Therefore, their payloads are constrained by size, weight, and power (SWaP). Thus, designing edge-side signal processing architectu…
  europepmc 2026 置信度 0.80
• LightIN: a versatile silicon-integrated photonic field programmable gate array with an intelligent configuration framework for next-generation AI clusters.
  europepmc 2026 置信度 0.80
• Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach.
  europepmc 2023 置信度 0.80
• Wafer-scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing.
  europepmc 2025 置信度 0.80
• A Selective Deposition Strategy of Ultrathin Metal Layer on Sub-Micrometer-Pitch Cu Interconnection for Low-Temperature Hybrid Bonding.
  europepmc 2026 置信度 0.80
• Electronic Chip Package and Co-Packaged Optics (CPO) Technology for Modern AI Era: A Review.
  europepmc 2025 置信度 0.80
• Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems.
  europepmc 2023 置信度 0.80
• Underfill: A Review of Reliability Improvement Methods in Electronics Production.
  europepmc 2025 置信度 0.80
• Hundred-layer photonic deep learning.
  europepmc 2025 置信度 0.80
• Advances in waveguide to waveguide couplers for 3D integrated photonic packaging.
  europepmc 2026 置信度 0.80
• Heterogeneous Integration Technology Drives the Evolution of Co-Packaged Optics.
  europepmc 2025 置信度 0.80
• Identification and Evolution of Core Technologies in the Chip Field Based on Patent Networks.
  europepmc 2025 置信度 0.80
• Integrated electronic controller for dynamic self-configuration of photonic circuits.
  europepmc 2025 置信度 0.80
• Nanoscale Silicon Fingerprints for Counterfeit Prevention in Microchips.
  europepmc 2025 置信度 0.80
• GHz-rate optical phase shift in light-matter interaction-engineered, silicon-ferroelectric nematic liquid crystals.
  europepmc 2025 置信度 0.80
• Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling.
  europepmc 2024 置信度 0.80
• Emerging Copper-to-Copper Bonding Techniques: Enabling High-Density Interconnects for Heterogeneous Integration.
  europepmc 2025 置信度 0.80
• Overview of Research Progress and Application Prospects of Thermal Test Chips.
  The development of semiconductor processes and advanced packaging technology has promoted significant advancements in the miniaturization and integration of electronic devices and systems. However, these developments present substantial challenges to the therm…
  pubmed Ju L, Jiang P, Ren Y, Liu R 等 2025 置信度 0.82
• Progress in Research on Co-Packaged Optics.
  europepmc 2024 置信度 0.80
• Nanophotonic Materials and Devices: Recent Advances and Emerging Applications.
  europepmc 2025 置信度 0.80
• Effect of Ag, Sn, and SiCN Surface Coating Layers on the Reliability of Nanotwinned Cu Redistribution Lines Under Temperature Cycling Tests.
  europepmc 2024 置信度 0.80
• Advanced Electronic Packaging Technology: From Hard to Soft.
  europepmc 2023 置信度 0.80
• Nature of the Metal Insulator Transition in High-Mobility 2D_Si-MOSFETs.
  europepmc 2023 置信度 0.80
• Photonic-electronic arbitrary-waveform generation using quadrature multiplexing and active optical-phase stabilization.
  europepmc 2025 置信度 0.80
• Advancing Thermal Management Technology for Power Semiconductors through Materials and Interface Engineering.
  Power semiconductors and chips are essential in modern electronics, driving applications from personal devices and data centers to energy technologies, vehicles, and Internet infrastructure. However, efficient heat dissipation remains a critical challenge, dir…
  pubmed Li M, Li S, Zhang Z, Su C 等 2025 置信度 0.82
• Roadmapping the next generation of silicon photonics.
  europepmc 2024 置信度 0.80
• Technological Advances and Medical Applications of Implantable Electronic Devices: From the Heart, Brain, and Skin to Gastrointestinal Organs.
  Implantable electronic devices are driving innovation in modern medical technology and have significantly improved patients' quality of life. This review comprehensively analyzes the latest technological trends in implantable electronic devices used in major o…
  pubmed Lee J, Han SY, Kwon YW 2025 置信度 0.82
• Fabrication of high aspect ratio, non-line-of-sight vias in silicon carbide by a two-photon absorption method.
  europepmc 2024 置信度 0.80
• Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review.
  europepmc 2023 置信度 0.80
• What is next for LLMs? Pushing the boundaries of next-gen AI computing hardware with photonic chips.
  Large language models (LLMs) are rapidly pushing the limits of contemporary computing hardware. For example, training GPT-3 has been estimated to consume around 1,300 MWh of electricity, and projections suggest future models may require city-scale (gigawatt) p…
  europepmc 2025 置信度 0.80
• Secure and Intelligent Low-Altitude Infrastructures: Synergistic Integration of IoT Networks, AI Decision-Making and Blockchain Trust Mechanisms.
  europepmc 2025 置信度 0.80
• Human-Centric, Three Dimensional Micro Light-Emitting Diodes for Cosmetic and Medical Phototherapy.
  Phototherapy based on micro light-emitting diodes (µLEDs) has gained enormous attention in the medical field as a patient-friendly therapeutic method due to its advantages of minimal invasiveness, fewer side effects, and versatile device form factors with…
  pubmed Nam KY, Kim MS, An J, Min S 等 2025 置信度 0.82
• An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning.
  europepmc 2023 置信度 0.80
• Beyond the Silicon Plateau: A Convergence of Novel Materials for Transistor Evolution.
  europepmc 2025 置信度 0.80
• The Roadmap of 2D Materials and Devices Toward Chips.
  europepmc 2024 置信度 0.80
• The planar anodic Al₂O₃-ZrO₂ nanocomposite capacitor dielectrics for advanced passive device integration.
  europepmc 2023 置信度 0.80
• Technology Roadmap for Flexible Sensors.
  europepmc 2023 置信度 0.80
• Layer-Scale and Chip-Scale Transfer Techniques for Functional Devices and Systems: A Review.
  europepmc 2021 置信度 0.80
• Recent Advances and Trends in Advanced Packaging
  In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discusse…
  openalex John H. Lau 2022-01-18 置信度 0.72 Chip-scale packageFlip chipPackaging engineeringWafer-level packagingFan-out
• Advanced packaging of chiplets for future computing needs
  openalex Debendra Das Sharma, Ravi Mahajan, Ravi V. Mahajan 2024-06-27 置信度 0.72 Computer scienceBusinessSystems engineeringEngineering
• High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
  The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced pac…
  openalex Shenggao Li, Mu-Shan Lin, Wei‐Chih Chen, Chien-Chun Tsai 等 2024-01-01 置信度 0.72 Electronic packagingIntegrated circuit packagingComputer scienceBandwidth (computing)Manufacturing engineering
• Advanced HDFO Packaging Solutions for Chiplets Integration in HPC Application
  As the industry enters the digital transformation and exascale computing era, massive compute with high frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising a problem o…
  openalex Lihong Cao Teck Lee, Yung-Shun Chang, SimonYL Huang, J. Salenc ̧on 等 2021-06-01 置信度 0.72 Computer scienceSystem in packageSilicon on insulatorWaferChip
• Chiplet Heterogeneous Integration Technology—Status and Challenges
  As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure…
  openalex Tao Li, Jie Hou, Jinli Yan, Rulin Liu 等 2020-04-20 置信度 0.72 Merge (version control)ReuseComputer scienceProcess (computing)Engineering
• Advanced Packaging Technology Platforms for Chiplets and Heterogeneous Integration
  As Moore’s law continues to challenge the foundry companies to increase transistor density, the exponential cost of silicon scaling has created an inflection point for the industry. The high development cost and lower yields for advanced Si nodes are challengi…
  openalex Lihong Cao 2022-12-03 置信度 0.72 Power integrityComputer sciencePackage on packageReuseSystem in package
• TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O
  In this article, we present TeraPHY, a monolithic electronic-photonic chiplet technology for low power and low latency, multi-Tb/s chip-to-chip communications. Integration of the TeraPHY optical technology with open source advanced interconnect bus interface e…
  openalex Mark T. Wade, Erik Anderson, Shahab Ardalan, Pavan Bhargava 等 2020-02-24 置信度 0.72 Computer scienceInterconnectionEmbedded systemBandwidth (computing)Low latency (capital markets)
• Advanced Packaging Design Platform for Chiplets and Heterogeneous Integration
  Chiplets integration offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization. Various advanced packaging technologies such as 2.5D Si TSV interposer, Fanout RDL organic interposer and 3D hybrid bonding have been…
  openalex Lihong Cao, Chen-Chao Wang, Chih-Yi Huang, Hung-Chun Kou 2023-05-01 置信度 0.72 InterposerInterconnectionPackaging engineeringFootprintEmbedded system
• Chiplet-based System PSI Optimization for 2.5D/3D Advanced Packaging Implementation
  In this work, we propose a novel chiplet platform for 2.5D/3D IC Integration. Given specific design requirements, the Samsung chipletadvanced platform engine (SCAPE) can provide an integrated image of suitable advanced packaging solutionsfrom multi-chip module…
  openalex Yoonjae Hwang, Sungwook Moon, Seungki Nam, Jeong HoonAhn 2022-05-01 置信度 0.72 InterposerPower integrityComputer scienceInterconnectionEmbedded system
• Modular Routing Design for Chiplet-Based Systems
  System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to tightly …
  openalex Jieming Yin, Zhifeng Lin, Onur Kayıran, Matthew Poremba 等 2018-06-01 置信度 0.72 Computer scienceModular designInterposerRouting (electronic design automation)Correctness
• Semiconductor Advanced Packaging
  openalex John H. Lau 2021-01-01 置信度 0.72 SemiconductorOptoelectronicsMaterials scienceComputer science
• High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express
  Abstract Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and …
  openalex Debendra Das Sharma, Gerald Pasdast, Sathya Tiagaraj, Kemal Aygün 2024-02-19 置信度 0.72 InterconnectionPackage designPower (physics)Computer scienceElectronic engineering
• Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package
  In this paper, we design and analyze the Universal Chiplet Interconnect Express (UCIe) channel considering signal integrity (SI) in silicon interposer for advanced package. In a chiplet system, various chips from other vendors are integrated into one package u…
  openalex Taein Shin, Keunwoo Kim, Hyunwook Park, Boogyo Sim 等 2023-12-12 置信度 0.72 InterposerSignal integrityInterconnectionSystem in packagePackage design
• Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)
  Emerging applications such as machine learning (ML) and artificial intelligence (AI) require more computing capabilities that ought to be distributed and have access to large memory and storage, while the systems need to be energy efficient and low-cost. The i…
  openalex Mihai Rotaru, Wei Tang, Rahul Dutta, Zhengya Zhang 2021-06-01 置信度 0.72 Computer scienceScalabilityWafer-level packagingInterposerEmbedded system
• Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging
  Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution…
  openalex Hongwei Liu, Yuan Du, Bo Pu, Guojun Yuan 等 2025-11-24 置信度 0.72 TerminologyDomain (mathematical analysis)Computer scienceSystems engineeringField (mathematics)
• Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE
  More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept …
  openalex Takafumi Fukushima 2021-06-13 置信度 0.72 Wafer-level packagingSystem integrationFan-outComputer sciencePackaging engineering
• Study of Large Exposure Field Lithography for Advanced Chiplet Packaging
  Demand for computers, GPUs and FPGAs and AI chips continues to grow as more systems demand higher computing power including AI processing and deep learning. To meet the performance and bandwidth requirements of the AI chips it is necessary to increase the chip…
  openalex Hiromi Suda, Douglas Shelton, Hiroki Takada, Yoshio Gotō 等 2022-05-01 置信度 0.72 OverlayComputer scienceLithographyStepperChip
• Advanced System in Package Enabled by Wafer Level Heterogeneous Integration of Chiplets
  Wafer level Heterogeneous Integration(HI) is enabling the semiconductor industry to continue packing increasing functionality into power-performance-form factor-cost (PPFC) optimized advanced System in Package (SiP) which addresses wide ranging market requirem…
  openalex S. Bhattacharya, Teck-Guan Lim, D. Ho, K. J. Chui 等 2022-12-03 置信度 0.72 System in packageAutomotive industryWaferSemiconductor industrySystem integration
• Chiplet actuary
  Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. I…
  openalex Yinxiao Feng, Kaisheng Ma 2022-07-10 置信度 0.72 ReuseComputer scienceChipActuarySystem on a chip
• Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe)
  openalex Yuxuan Fan, Yunyan Zhou, Qidong Wang, Bo Lei 等 2025-03-28 置信度 0.72 InterconnectionBridge (graph theory)Package designEngineeringElectronic engineering
• Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer
  Chiplet-based packaging technology integrates multiple heterogeneous dies with different functions and materials into a single system as a LEGO-based approach using advanced packaging technology. However, it also brings new challenges in the thermal design asp…
  openalex Minghao Zhou, Li Li, Fengze Hou, He Guoqiang 等 2022-05-30 置信度 0.72 InterposerHeat sinkMaterials scienceHeat transfer coefficientThermal grease