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• Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems
  As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target.…
  arxiv Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu 等 2022-09-30T19:45:04Z 置信度 0.78 cs.CRcs.AR
• Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
  Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been able to keep up with the dema…
  arxiv Aleksa Deric, Kyle Mitard, Shahin Tajik, Daniel Holcomb 2024-05-23T17:38:13Z 置信度 0.78 cs.CR
• FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
  Chiplet-based systems are rapidly gaining traction in the market. Two packaging options for such systems are the established organic substrates and the emerging glass substrates. These substrates are used to implement the inter-chiplet interconnect (ICI), whic…
  arxiv Patrick Iff, Maciej Besta, Torsten Hoefler 2025-04-28T15:07:36Z 置信度 0.78 cs.AR
• CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
  The exponential growth of AI has created unprecedented demand for computational resources, pushing chip designs to the limit while simultaneously escalating the environmental footprint of computing. As the industry transitions toward heterogeneous integration …
  arxiv Chetan Choppali Sudarshan, Jiajun Hu, Aman Arora, Vidya A. Chhabria 2026-03-04T09:30:45Z 置信度 0.78 cs.ARcs.ET
• Advanced Accelerator Concepts: From Birth to High Impact Science
  This recounting of the history of the last three-and-a-half decades of advanced accelerator concepts is offered from a decidedly parochial point of view -- that of the career of the author, Prof. James Rosenzweig of the UCLA Dept. of Physics and Astronomy. Thi…
  arxiv James Rosenzweig 2023-02-23T20:18:33Z 置信度 0.78 physics.acc-ph
• Security Assessment of Interposer-based Chiplet Integration
  With transistor scaling reaching its limits, interposer-based integration of dies (chiplets) is gaining traction. Such an interposer-based integration enables finer and tighter interconnect pitch than traditional system-on-packages and offers two key benefits:…
  arxiv Mohammed Shayan, Kanad Basu, Ramesh Karri 2020-10-25T16:29:47Z 置信度 0.78 cs.CRcs.AR
• ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication
  2.5D chiplet systems have been proposed to improve the low manufacturing yield of large-scale chips. However, connecting the chiplets through an electronic interposer imposes a high traffic load on the interposer network. Silicon photonics technology has shown…
  arxiv Ebadollah Taheri, Sudeep Pasricha, Mahdi Nikdast 2022-08-08T16:00:37Z 置信度 0.78 cs.ARcs.ETphysics.optics
• REED: Chiplet-Based Accelerator for Fully Homomorphic Encryption
  Fully Homomorphic Encryption (FHE) enables privacy-preserving computation and has many applications. However, its practical implementation faces massive computation and memory overheads. To address this bottleneck, several Application-Specific Integrated Circu…
  arxiv Aikata Aikata, Ahmet Can Mert, Sunmin Kwon, Maxim Deryabin 等 2023-08-05T14:04:39Z 置信度 0.78 cs.CR
• An Integrated Circuit Compatible Compact Package for Thermal Gas Flowmeters
  An original packaging method suitable for integrated thermal mass flow sensors is presented. The method consists in the application of a plastic transparent adapter to the chip surface. The adapter is sealed to the chip surface by means of a thermal procedure.…
  arxiv P. Bruschi, V. Nurra 2008-02-21T13:23:39Z 置信度 0.78 cs.OH
• Selection of High Strength Encapsulant for MEMS Devices Undergoing High Pressure Packaging
  Deflection behavior of several encapsulant materials under uniform pressure was studied to determine the best encapsulant for MEMS device. Encapsulation is needed to protect movable parts of MEMS devices during high pressure transfer molded packaging process. …
  arxiv A. A. Hamzah, Y. Husaini, Y. Husaini, B. Y. Majlis 等 2008-02-21T13:40:31Z 置信度 0.78 cs.OH
• Design Guidelines for In-line X-ray Inspection in Advanced Packaging Technology: A CoWoS Case Study
  The shift towards advanced packaging technologies, including 2.5D and 3D integration, addresses the limitations of traditional methods while meeting increasing demands for performance, miniaturization, and efficiency. These methods enhance functionality and su…
  arxiv Katayoon Yahyaei, M Shafkat M Khan, Guillermo Cadima, Himanandhan Reddy Kottur 等 2026-06-24T22:41:23Z 置信度 0.78 eess.IV
• CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems
  With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to a single die design, now there are options for 2.5D and 3D stacking along with…
  arxiv Alexander Graening, Jonti Talukdar, Saptadeep Pal, Krishnendu Chakrabarty 等 2025-03-20T00:07:10Z 置信度 0.78 cs.AR
• On Frequency Response Function Identification for Advanced Motion Control
  A key step in control of precision mechatronic systems is Frequency Response Function (FRF) identification. The aim of this paper is to illustrate relevant developments and solutions for FRF identification for advanced motion control. Specifically dealing with…
  arxiv Enzo Evers, Robbert Voorhoeve, Tom Oomen 2020-06-18T09:14:43Z 置信度 0.78 eess.SY
• 2.5D Root of Trust: Securing the Chiplet Ecosystem
  The semiconductor industry is rapidly transitioning from monolithic systems-on-chip toward heterogeneous, multi-vendor 2.5D chiplet ecosystems integrated via silicon interposers. While this paradigm shift offers immense benefits in yield, cost, and time-to-mar…
  arxiv Charles Williams, Mohammed Nabeel, Gino Chacon, Ozgur Sinanoglu 等 2026-06-20T19:19:54Z 置信度 0.78 cs.CRcs.AR
• AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems
  The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market solutions for AI and high-performance computing. However, multi-vendor assembly in post-fabrication environ…
  arxiv Ishraq Tashdid, Tasnuva Farheen, Sazadur Rahman 2025-08-18T15:51:48Z 置信度 0.78 cs.CR
• Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
  Modern AI acceleration faces a fundamental challenge: conventional assumptions about memory requirements, batching effectiveness, and latency-throughput tradeoffs are systemwide generalizations that ignore the heterogeneous computational patterns of individual…
  arxiv Haoran Jin, Jirong Yang, Yunpeng Liu, Barry Lyu 等 2025-10-10T00:07:07Z 置信度 0.78 cs.AR
• Advanced System Integration: Analyzing OpenAPI Chunking for Retrieval-Augmented Generation
  Integrating multiple (sub-)systems is essential to create advanced Information Systems (ISs). Difficulties mainly arise when integrating dynamic environments across the IS lifecycle. A traditional approach is a registry that provides the API documentation of t…
  arxiv Robin D. Pesl, Jerin G. Mathew, Massimo Mecella, Marco Aiello 2024-11-29T16:09:43Z 置信度 0.78 cs.SEcs.AI
• Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging
  As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration. This paper…
  arxiv Himanandhan Reddy Kottur, Pavanbabu Arjunamahanthi, M. Shafkat M. Khan, Liton Kumar Biswas 等 2026-06-24T22:33:33Z 置信度 0.78 cs.ARcs.CReess.IV
• A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
  Transformers have revolutionized deep learning and generative modeling, enabling advancements in natural language processing tasks. However, the size of transformer models is increasing continuously, driven by enhanced capabilities across various deep learning…
  arxiv Harsh Sharma, Pratyush Dhingra, Janardhan Rao Doppa, Umit Ogras 等 2023-12-18T23:27:28Z 置信度 0.78 cs.ARcs.DC
• Codesign of quantum error-correcting codes and modular chiplets in the presence of defects
  Fabrication errors pose a significant challenge in scaling up solid-state quantum devices to the sizes required for fault-tolerant (FT) quantum applications. To mitigate the resource overhead caused by fabrication errors, we combine two approaches: (1) leverag…
  arxiv Sophia Fuhui Lin, Joshua Viszlai, Kaitlin N. Smith, Gokul Subramanian Ravi 等 2023-04-29T01:06:52Z 置信度 0.78 quant-ph
• CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure
  Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to design ASIC accelerators to mitigate t…
  arxiv Sangpyo Kim, Jongmin Kim, Jaeyoung Choi, Jung Ho Ahn 2023-08-09T11:41:56Z 置信度 0.78 cs.ARcs.CR
• Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration
  Failure analysis is being reshaped by heterogeneous integration, chiplet-based architectures, hybrid bonding, backside technologies, & increasingly buried package structures. To examine how practitioners view this transition, an anonymous survey was distri…
  arxiv Himanandhan Reddy Kottur, Nusra Akter Takia, Mahamudul Hassan Fuad, Istiaq Firoz Shiam 等 2026-06-20T16:59:36Z 置信度 0.78 cs.SEcs.CVeess.IV
• CHICO-Agent: An LLM Agent for the Cross-layer Optimization of 2.5D and 3D Chiplet-based Systems
  The rapid growth of large language models (LLMs) and AI workloads has pushed monolithic silicon to its reticle and economic limits, accelerating the adoption of 2.5D/3D chiplet systems. However, these systems increase design complexity by requiring co-design a…
  arxiv Qihang Wu, Aman Arora, Vidya A. Chhabria 2026-04-20T19:17:24Z 置信度 0.78 cs.AR
• A high entropy alloy as very low melting point solder for advanced electronic packaging
  SnBiInZn based high entropy alloy (HEA) was studied as a low reflow temperature solder with melting point around 80 oC. The wetting angle is about 52o after reflow at 100 oC for 10 min. The interfacial intermetallic compound (IMC) growth kinetics was measured …
  arxiv Yingxia Liua, Li Pu, Yong Yang, Quanfeng He 等 2020-06-02T02:07:40Z 置信度 0.78 physics.app-phcond-mat.mtrl-sci
• A Fully Parameterized Fem Model for Electromagnetic Optimization of an RF Mems Wafer Level Package
  In this work, we present a fully parameterized capped transmission line model for electromagnetic optimization of a wafer level package (WLP) for RF MEMS applications using the Ansoft HFSS-TM electromagnetic simulator. All the degrees of freedom (DoF's) in the…
  arxiv J. Iannacci, J. Tian, R. Gaddi, A. Gnudi 等 2008-02-21T13:21:58Z 置信度 0.78 cs.OH
• ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators
  Chiplet-based DNN accelerators provide a scalable path to balance performance and yield for modern AI workloads. However, such systems face critical challenges in area and thermal constraints. Design space optimization should jointly consider fine-grained task…
  arxiv Jian Peng, Hanwei Fan, Jingbo Jiang, Lin Jiang 等 2026-07-08T07:30:13Z 置信度 0.78 cs.AR
• Advances in quantum dense coding
  Quantum dense coding is one of the most important protocols in quantum communication. It derives from the idea of using quantum resources to boost the communication capacity and now serves as a key primitive across a variety of quantum information protocols. H…
  arxiv Yu Guo, Bi-Heng Liu, Chuan-Feng Li, Guang-Can Guo 2019-04-28T03:37:32Z 置信度 0.78 quant-ph
• Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception
  We study the application of emerging chiplet-based Neural Processing Units to accelerate vehicular AI perception workloads in constrained automotive settings. The motivation stems from how chiplets technology is becoming integral to emerging vehicular architec…
  arxiv Mohanad Odema, Luke Chen, Hyoukjun Kwon, Mohammad Abdullah Al Faruque 2024-11-24T22:59:11Z 置信度 0.78 cs.ARcs.AIcs.DCcs.PF
• Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators
  Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteristics. In this paper, we aim to analyse the potential bottlenecks cau…
  arxiv Mariam Musavi, Emmanuel Irabor, Abhijit Das, Eduard Alarcon 等 2024-10-29T17:23:25Z 置信度 0.78 cs.AR
• Next Generation Advanced Transceiver Technologies for 6G and Beyond
  To accommodate new applications such as extended reality, fully autonomous vehicular networks and the metaverse, next generation wireless networks are going to be subject to much more stringent performance requirements than the fifth-generation (5G) in terms o…
  arxiv Changsheng You, Yunlong Cai, Yuanwei Liu, Marco Di Renzo 等 2024-03-25T06:41:25Z 置信度 0.78 cs.ITeess.SP
• DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation
  Constructing behavioral-level chiplet models (e.g., SystemC) is crucial for early-stage heterogeneous architecture exploration. Traditional manual modeling is notoriously time-consuming and error-prone. Recently, Large Language Models (LLMs) have demonstrated …
  arxiv Yiwei Wu, Yifan Wu, Yunhao Xiong, Dengwei Zhao 等 2026-03-22T12:23:38Z 置信度 0.78 cs.AR
• Summary of Working Group 8: Advanced and Novel Accelerators for High Energy Physics
  We briefly summarize the work and discussions that occurred during the Working Group 8 sessions of the EAAC 2017, dedicated to advanced and novel accelerators for high energy physics applications.
  arxiv B. Cros, P. Muggli, C. B. Schroeder, C. Tang 2017-12-22T08:46:05Z 置信度 0.78 physics.acc-ph
• Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
  Multi-chiplet architectures enabled by glass interposer offer superior electrical performance, enable higher bus widths due to reduced crosstalk, and have lower capacitance in the redistribution layer than current silicon interposer-based systems. These advant…
  arxiv Harsh Sharma, Janardhan Rao Doppa, Umit Y. Ogras, Partha Pratim Pande 2025-07-24T02:26:08Z 置信度 0.78 cs.AR
• A Generic Surface Micromachining Module for Mems Hermetic Packaging at Temperatures Below 200 degrees C
  This paper presents the different processing steps of a new generic surface micromachining module for MEMS hermetic packaging at temperatures around 180 degrees C based on nickel plating and photoresist sacrificial layers. The advantages of thin film caps are …
  arxiv R. Hellin-Rico, J. -P. Celis, K. Baert, C. Van Hoof 等 2007-11-21T10:03:52Z 置信度 0.78 cs.OH
• Quantum-Chiplet: A Novel Python-Based Efficient and Scalable Design Methodology for Quantum Circuit Verification and Implementation
  Analysis and verification of quantum circuits are highly challenging, given the exponential dependence of the number of states on the number of qubits. For analytical derivation, we propose a new quantum polynomial representation (QPR) to facilitate the analys…
  arxiv Yu-Ting Kao, Hao-Yu Lu, Yeong-Jar Chang, Darsen Lu 2025-03-13T05:12:41Z 置信度 0.78 quant-ph
• Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
  To address increasing compute demand from recent multi-model workloads with heavy models like large language models, we propose to deploy heterogeneous chiplet-based multi-chip module (MCM)-based accelerators. We develop an advanced scheduling framework for he…
  arxiv Mohanad Odema, Hyoukjun Kwon, Mohammad Abdullah Al Faruque 2023-12-14T23:45:55Z 置信度 0.78 cs.ARcs.AIcs.DC
• Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
  Heterogeneous chiplets have been proposed for accelerating high-performance computing tasks. Integrated inside one package, CPU and GPU chiplets can share a common interconnection network that can be implemented through the interposer. However, CPU and GPU app…
  arxiv Siamak Biglari, Ruixiao Huang, Hui Zhao, Saraju Mohanty 2024-06-01T22:25:57Z 置信度 0.78 cs.AR
• US Microelectronics Packaging Ecosystem: Challenges and Opportunities
  The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the s…
  arxiv Rouhan Noor, Himanandhan Reddy Kottur, Patrick J Craig, Liton Kumar Biswas 等 2023-10-18T01:36:14Z 置信度 0.78 eess.SYcs.CR
• PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration
  This paper presents a 3D-stacked chiplets based large language model (LLM) inference accelerator, consisting of non-volatile in-memory-computing processing elements (PEs) and Inter-PE Computational Network (IPCN), interconnected via silicon photonic to effecti…
  arxiv Yue Jiet Chong, Yimin Wang, Zhen Wu, Xuanyao Fong 2025-11-06T04:15:20Z 置信度 0.78 cs.AR
• LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs
  Data movement overheads increase the inference latency of state-of-the-art large language models (LLMs). These models commonly use the bfloat16 (BF16) format for stable training. Floating-point standards allocate eight bits to the exponent, but our profiling r…
  arxiv Miao Sun, Alish Kanani, Kaushik Shroff, Umit Ogras 2026-03-16T17:48:30Z 置信度 0.78 cs.AR
• Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology
  Advances in nanosheet technologies have significantly increased power densities, exacerbating thermal management challenges in 2.5D/3D chiplet-based Systems-in-Package (SiP). While traditional thermal analyses often employ uniform power maps to simplify comput…
  arxiv Yukai Chen, Massimiliano Di Todaro, Bjorn Vermeersch, Herman Oprins 等 2025-08-04T10:53:39Z 置信度 0.78 cs.ET
• State-Of-The-Art of Advanced Packaging
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• Megachip: An Advanced Packaging Solution for Chiplet Integration
  We present our development of a novel heterogeneous chip-tiling approach that enables the realization of extremely large-area integrated circuits (ELAICs) or “Megachips”- containing tens of closely spaced small chiplets that are interconnected via redistributi…
  crossref Rabindra N. Das, Jason Plant, Matthew Ricci, Ryan Johnson 等 2025-02-17T11:20:13Z 置信度 0.70
• Trade-off Between Chiplet Dimensions and Packaging Parameters for Optimal Performance to Cost for Chiplet Based Heterogeneous Integration
  crossref Krutikesh Sahoo, Max Zhai, Subramanian Iyer 2025-03-11T17:30:44Z 置信度 0.70
• Chiplet Design and Heterogeneous Integration Packaging
  crossref John Lau, Xuejun Fan 2025-05-18T06:02:39Z 置信度 0.70
• Investigation of RF Characteristics of Inter-Chiplet Connections for Advanced HPC Packaging Solutions
  crossref Alexander Gäbler, Xunqi Zhang, Uwe Maaß, Marius Adler 等 2025-11-10T18:45:25Z 置信度 0.70
• Investigation of RF Characteristics of Chiplet to PCB Transitions for Advanced HPC Packaging Solutions
  crossref Alexander Gäbler, Uwe Maaß, Ivan Ndip 2024-10-15T17:19:58Z 置信度 0.70
• Exploring Bond Strength for Advanced Chiplet with Hybrid Bonding
  crossref Junya Fuse, Tomoya Iwata, Yuki Yoshihara, Marie Sano 等 2024-03-18T14:54:03Z 置信度 0.70
• Cost Analysis of Fan-out Processes for Chiplet Packaging
  When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that …
  crossref Amy Lujan 2024-02-28T11:55:29Z 置信度 0.70
• Heterogeneous Packaging Technologies for Chiplet and Memory Integration
  To meet the High-Performance Computing (HPC) and Artificial Intelligence (AI) market demands of ever higher performance, lower power consumption, wider memory bandwidth with reduced latency, the interconnects connecting D2D in advanced packages are getting eve…
  crossref Yan Li, WooPoung Kim 2025-01-30T21:37:35Z 置信度 0.70
• Chiplets Lateral Communications
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• Selecting Strip-Based or Singulated Laminates in Chiplet Packaging
  Deciding whether to pursue strip-based or singulated laminate substrates for chiplet packaging has become more important as technological capabilities of both architectures have grown enough to overlap broadly. This paper investigates, analyzes, and prioritize…
  crossref Brendan C. Wells 2025-02-17T16:20:18Z 置信度 0.70
• Cu-Cu Hybrid Bonding
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• Cost Analysis of Fan-out Processes for Chiplet Packaging
  When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that …
  crossref Amy Palesko Lujan 2024-03-01T17:55:24Z 置信度 0.70
• Electrical Performance of Interconnects in an Organic Interposer Targeted for Chiplet Applications
  crossref Ying Ying Lim, Shunsuke Nemoto, Wei Feng, Ken-ichi Nomura 等 2026-03-03T20:50:33Z 置信度 0.70
• Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging ^*
  crossref Partho Bhoumik, Arjun Chaudhuri, Sandeep Kumar Goel, Krishnendu Chakrabarty 2025-11-03T18:42:34Z 置信度 0.70
• Micro-scale chiplet assembly control with chiplet-to-chiplet potential interaction
  crossref Ion Matei, Anne Plochowietz, Johan de Kleer, John S. Baras 2022-02-01T20:50:18Z 置信度 0.70
• Boundary-Scan Supporting Chiplet Packaging
  crossref 2022-12-31T22:13:14Z 置信度 0.70
• Development of Automotive Chiplet SoC
  crossref Nobuaki Kawahara 2026-06-10T19:59:01Z 置信度 0.70
• Multiple System and Heterogeneous Integration with TSV-Interposers
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• A Global-Local Finite Element Simulation Approach for Early Failure Detection in Chiplet Packaging
  crossref C.A. Yang, W.F. Wang, K.N. Chiang 2025-12-16T18:30:06Z 置信度 0.70
• Beyond Moore’s law: the chiplet revolution in semiconductor packaging
  crossref Yasumitsu Orii 2026-04-09T22:03:08Z 置信度 0.70
• Active Measurement Wafer for Thermal Characterization in Chiplet-Based Systems
  crossref Andy Heinig 2026-02-24T20:55:10Z 置信度 0.70
• Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging
  crossref Li Kangrong, Mihai Dragos Rotaru 2021-01-14T22:59:35Z 置信度 0.70
• Mechanical Reliability in the Replaceable Integrated Chiplet Assembly
  crossref 2025-12-30T07:47:56Z 置信度 0.70
• Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation
  crossref Xuguang Yuan, Jiangyuan Gu, Qidie Wu, Yang Hu 等 2026-06-04T19:53:10Z 置信度 0.70
• Multiple System and Heterogeneous Integration with TSV-Less Interposers
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• Design of Chiplet Interconnects Considering Crosstalk Induced from Meshed Ground Plane
  crossref Jiwoon Moon, Yuchul Jung, Jonghyeon Lee, Taei Kim 等 2026-03-03T20:50:33Z 置信度 0.70
• Thermal-mechanical coupling simulation of Chiplet 2.5D packaging based on chiplet distribution and Full Copper Interconnection
  crossref Shizhen Li, Chenshan Gao, Xu Liu, Huaiyu Ye 等 2026-05-15T02:40:02Z 置信度 0.70
• Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration
  crossref John H. Lau 2023-03-27T12:03:02Z 置信度 0.70
• Chiplet Packaging Technology for the 2 nm-Generation Advanced Semiconductor
  crossref Katsuya KIKUCHI 2025-12-09T22:10:51Z 置信度 0.70
• The Significance of Thermal-Aware Universal Chiplet Interconnect Express (UCIe) Interface Design in 2.5D/3D ICs
  crossref Keeyoung Son, Keunwoo Kim, Seonguk Choi, Jiwon Yoon 等 2024-03-19T18:12:25Z 置信度 0.70
• Signal Integrity Analysis of Interconnect Structures in 2.1D Thin Film Packaging for Chiplet Integration
  crossref Xiao Cui, Yan Luo, Haotian Li, Junwei Ma 等 2025-09-17T17:29:31Z 置信度 0.70
• Evolution of Chiplet packaging architectures advancing AI and HPC growth
  crossref Daniel Ng 2024-10-16T00:21:36Z 置信度 0.70
• Bunch of Wires Interface PHY Design for Multi-Chiplet Systems
  crossref Maudood Ahmed, Muhammad Waqas Chaudhary, Andy Heinig 2022-01-05T20:42:25Z 置信度 0.70
• Optical Pitch Transformer Chiplet: Enhancing Packaging Beachfront Density
  crossref How Yuan Hwang, Xiuyun He, Peter O'Brien 2026-02-26T20:42:16Z 置信度 0.70
• EDA Solution for Chiplet and 3D-IC Design
  crossref Ksenia Roze, Mark Gerber 2026-06-10T19:59:01Z 置信度 0.70
• Signal Integrity Analysis of High-Speed Chiplet Interconnection Considering Surface Roughness Based on Huray Model
  crossref Jonghyeon Lee, Jiwoon Moon, Yuchul Jung, Uichan Kim 等 2026-03-03T20:50:33Z 置信度 0.70
• Multi-Chiplet Placement Design for 3D Integration
  crossref Mak Hoi Chau, Chung-Long Pan, Yu-Jung Huang 2022-12-08T18:40:25Z 置信度 0.70
• Holistic Chiplet Packaging Approach
  crossref Tanja Braun, Karl-Friedrich Becker, Michael Schiffer, Rolf Aschenbrenner 等 2026-05-06T19:38:04Z 置信度 0.70
• Boundary-Scan Technology for Chiplet Test
  crossref Shuichi Kameyama 2024-06-30T22:20:40Z 置信度 0.70
• Fine-Pitch Hybrid Bonding and TOV Fusion Bonding for Scalable Chiplet Architecture and System Disaggregation
  ABSTRACT As semiconductor devices grow in complexity and transistor scaling approaches physical limits, traditional monolithic chip designs face significant challenges, including reduced manufacturing yields and escalating costs. To overcome these limitations,…
  crossref Srinidhi Ramamoorthy, Fred Fishburn 2026-05-13T02:09:43Z 置信度 0.70
• Maskless Lithography Optimized for Heterogeneous and Chiplet Integration
  ABSTRACT Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in …
  crossref B. Matuskova, B. Považay, R. Holly, F. Bögelsack 等 2025-12-01T20:36:09Z 置信度 0.70
• Physics-Informed Graph Convolutional Neural Network for Scalable, and Accurate Thermal Analysis of 2.5D Chiplet-Based Systems
  crossref Rahul Sahay, Nagarajan Raghavan 2026-02-24T20:55:10Z 置信度 0.70
• Connectivity-Guided Feasibility Masking for Efficient Chiplet Placement in 2.5D Packaging via Reinforcement Learning
  crossref Partha Pratim Kundu, Furen Zhuang, Sezin Ata Kircali, Yubo Hou 等 2026-02-24T20:55:10Z 置信度 0.70
• Chiplet Integration Technology by Suspended Bridge Architecture
  crossref Yoichiro Kurita 2023-06-30T18:16:49Z 置信度 0.70
• Chiplet Concept and Rapid Prototyping of 3D-IC
  crossref Takafumi Fukushima 2023-06-30T18:16:48Z 置信度 0.70
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• Chiplet Packaging and AI Defect Inspection
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