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• Numerical modeling of triple material gate stack gate all-around (TMGSGAA) MOSFET considering quantum mechanical effects
  crossref B. Padmanaban, R. Ramesh, D. Nirmal, S. Sathiyamoorthy 2015-02-16T12:35:17Z 置信度 0.70
• Gate-All-Around Nanosheet FET Device Simulation Methodology Using a Sentaurus TCAD
  crossref Anushka Singh, Archana Pandey 2023-12-06T17:21:48Z 置信度 0.70
• Gate-All-Around Technology is Coming.
  crossref Victor Moroz 2023-03-22T17:51:55Z 置信度 0.70
• Investigation on cylindrical gate-all-around (GAA) tunnel FETS scaling
  crossref M. Kessi, A. Benfdila, A. Lakhlef 2017-12-14T22:12:33Z 置信度 0.70
• Research of Gate-All-Around Field-Effect Transistors.
  This report provides an overview of GAA FETs also known as Gate-All-Around FETs, focusing on their introduction and limitations, based on a comprehensive review of current literature and online resources. GAA FETs represent an evolution of FinFET technology, w…
  crossref Lecheng Pan 2026-01-25T00:19:46Z 置信度 0.70
• Scaling Beyond 7nm Node: An Overview of Gate-All-Around FETs
  crossref Wei Hu, Feng Li 2021-07-26T21:03:41Z 置信度 0.70
• Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
  crossref Jae Sung Lee, Woo Young Choi, In Man Kang 2013-12-21T12:18:17Z 置信度 0.70
• Research of Gate-All-Around Field-Effect Transistors
  This report provides an overview of GAA FETs also known as Gate-All-Around FETs, focusing on their introduction and limitations, based on a comprehensive review of current literature and online resources. GAA FETs represent an evolution of FinFET technology, w…
  crossref Lecheng Pan 2024-10-29T19:52:05Z 置信度 0.70
• Design Space Exploration of 14nm Gate All around MOSFET
  crossref Rafeek Alas, Kiran Bailey 2016-03-17T20:28:41Z 置信度 0.70
• Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET
  The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variationa…
  crossref P. Vimala, N.R. Nithin Kumar 2019-08-27T14:27:23Z 置信度 0.70
• Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs
  crossref Mohammad Najmzadeh, Didier Bouvet, Wladek Grabinski, Adrian M. Ionescu 2011-09-21T16:17:53Z 置信度 0.70
• Review of: "The changes in the width of the nano transistor channel due to the field effect of the gate around can cause undesirable changes and loss of mobility"
  crossref Cita O,brain 2023-11-13T04:58:47Z 置信度 0.70
• An embedded gate gate-all-around FinFET for biosensing application
  crossref Hujun Jia, Wanli Yang, Weitao Cao, Linna Zhao 等 2024-08-31T03:42:44Z 置信度 0.70
• An investigation on a triple material double gate cylindrical gate all around (TMDG-CGAA) MOSFET for enhanced device performance
  crossref Asmita Menaria, Rahul Pandey, Ramesh Kumar 2020-06-03T21:15:33Z 置信度 0.70
• SiGe cantilever channel gate-all-around (GAA) fully depleted (FD) PMOSFET with high-¿ and metal gate
  crossref S.-H. Lee, S. Dey, S V. Joshi, P. Majhi 等 2007-11-06T15:40:09Z 置信度 0.70
• Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs
  crossref S. Kolberg, H. Børli, T.A. Fjeldly 2007-10-01T18:00:10Z 置信度 0.70
• Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET
  crossref Lining Zhang, Chenyue Ma, Jin He, Xinnan Lin 等 2010-04-21T04:44:50Z 置信度 0.70
• 3D Self-Consistent Quantum Transport Simulation for GaAs Gate-All-Around Nanowire Field-Effect Transistor with Elastic and Inelastic Scattering Effects
  crossref Han-Wei Hsiao, Yuh-Renn Wu 2018-10-08T05:50:26Z 置信度 0.70
• A Vertical Combo Spacer to Optimize Electrothermal Characteristics of 7-nm Nanosheet Gate-All-Around Transistor
  crossref Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi 2020-05-04T23:54:12Z 置信度 0.70
• On trap identification in triple-gate FinFETs and Gate-All-Around nanowire MOSFETs using low frequency noise spectroscopy
  crossref D. Boudier, B. Cretu, E. Simoen, A. Veloso 等 2017-07-25T21:38:00Z 置信度 0.70
• Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
  In this paper, gate-all-around (GAA) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials have been simulated and their characteristics have been optimized as a function of the high- k dielectric length ( L high k ). For the op…
  crossref Jae Sung Lee, Woo Young Choi, In Man Kang 2012-06-20T01:33:10Z 置信度 0.70
• Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor
  crossref Amol D. Gaidhane, Girish Pahwa, Amit Verma, Yogesh Singh Chauhan 2018-03-21T14:04:49Z 置信度 0.70
• Non-Fourier electrothermal fully coupled analysis of a 5 nm gate-all-around field-effect transistor based on density gradient theory
  In the post-Moore era, the three-dimensional fully surrounded channel structure of gate-all-around field-effect transistors (GAAFETs) significantly enhances gate control capabilities. However, its nanoscale features lead to severe overall self-heating effects …
  crossref Zhe Liu, Bo Hua Sun, Hai Hang Cui, Kai Sun 2025-02-07T09:39:36Z 置信度 0.70
• Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions
  crossref Dheeraj Sharma, Santosh Kumar Vishvakarma 2012-03-06T12:15:40Z 置信度 0.70
• Conical surrounding gate MOSFET: a possibility in gate-all-around family
  crossref B Jena, B S Ramkrishna, S Dash, G P Mishra 2016-02-12T09:14:06Z 置信度 0.70
• Design Optimization of InAs-Based Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (TFET)
  crossref Jae Hwa Seo, Young Jun Yoon, Young-Woo Jo, Dong-Hyeok Son 等 2016-08-20T15:59:39Z 置信度 0.70
• Gate level transistor sizing by nonlinear optimization.
  crossref Raymond Chow 2018-10-04T20:10:16Z 置信度 0.70
• Numerical modelling for triple hybrid gate optimization dielectric modulated junctionless gate all around SiNWFET based uricase and ChOX biosensor
  crossref Rishu Chaujar, Mekonnen Getnet Yirak 2024-06-18T01:02:32Z 置信度 0.70
• DIBL Mitigation Strategies in Gate-all-around Fets for Low Power Performance
  The high demand for low-power data processing in AI chips has necessitated the development of high-performance transistors. To suppress the critical drain-induced barrier lowering (DIBL) effect in gate-all-around field-effect transistors (GAAFETs), this paper …
  crossref Zirou Ji 2026-06-01T07:16:44Z 置信度 0.70
• Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices
  crossref Krutideepa Bhol, Biswajit Jena, Umakanta Nanda 2020-07-29T14:20:17Z 置信度 0.70
• (Invited) Doping Considerations for Finfet, Gate-All-Around, and Nanosheet Based Devices
  The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height …
  crossref Ray Duffy 2021-07-16T18:58:45Z 置信度 0.70
• Analytical subthreshold swing model of junctionless elliptic gate-all-around (GAA) FET
  <p>An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is diffi…
  crossref Hakkee Jung 2024-04-15T11:24:13Z 置信度 0.70
• Performance of γ-irradiated gate-all-around SOI MOS OTA amplifiers
  crossref A. Vandooren, P. Francis, D. Flandre, J.-P. Colinge 2002-11-23T01:47:57Z 置信度 0.70
• Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET
  Abstract In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region fo…
  crossref Amit Kumar, Anil Kumar Rajput, Manisha Pattanaik, Pankaj Srivast 2021-06-03T14:40:36Z 置信度 0.70
• Analytical threshold voltage model of gate all around triple metal tunnel FET
  crossref Navjeet Bagga, S. Dasgupta 2017-10-25T15:19:03Z 置信度 0.70
• Impact of Different Gate Dielectric Materials on Analog/RF Performance of Dielectric-Pocket Double Gate-All-Around (DP − DGAA) MOSFETs
  crossref Vaibhav Purwar, Rajeev Gupta, Himanshi Awasthi, Sarvesh Dubey 2022-01-27T00:03:36Z 置信度 0.70
• Nanobridge gate-all-around phototransistors for electro-optical OR gate circuit and frequency doubler applications
  crossref Jin Yong Oh, M. Saif Islam 2014-01-17T15:50:40Z 置信度 0.70
• Subthreshold Analytical Model of Asymmetric Gate Stack Triple Metal Gate all Around MOSFET (AGSTMGAAFET) for Improved Analog Applications
  crossref Arvind Ganesh, Kshitij Goel, Jaskeerat Singh Mayall, Sonam Rewari 2021-06-09T19:03:07Z 置信度 0.70
• Comparative Analysis of Different Materials for Gate-All-Around Nanowire FET
  crossref Salman Saleem, P Vimala 2022-06-16T19:38:00Z 置信度 0.70
• Quantum Dot Gate Field-Effect Transistor (QDGFET): Circuit Model and Ternary Logic Inverter
  crossref Supriya Karmakar 2013-11-20T10:17:51Z 置信度 0.70
• Temperature Dependent Sub threshold Drain Current Model for Junction less Gate all Around MOSFET with High-K Gate Stack
  crossref Suman Sharma, Rajni Shukla 2016-02-15T12:37:39Z 置信度 0.70
• Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET
  crossref Lining Zhang, Chenyue Ma, Jin He, Xinnan Lin 等 2010-07-07T08:52:15Z 置信度 0.70
• Asymmetrie Vacuum Gate Dielectric Schottky Barrier Gate all around MOSFET for ambipolarity reduction and improved hot carrier reliability
  crossref Manoj Kumar, Mridula Gupta, Subhasis Haldar, R.S. Gupta 2015-10-01T18:05:50Z 置信度 0.70
• Machine Learning Assisted Sensitivity of Triple-Material Gate -Stack Gate-All-Around (TM-GS-GAA) MOSFET based Biosensor
  crossref Rashmi Gupta, Neeraj Gupta, Arun Kumar Singh, Prashant Kumar 等 2025-05-29T17:06:14Z 置信度 0.70
• Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels
  crossref Tsung-Kuei Kang, Ta-Chuan Liao, Chun-Kai Wang 2012-05-31T18:40:47Z 置信度 0.70
• Design And Analysis Of Gate-All-Around (GAA) Triple Material Gate Charge Plasma Nanowire FET
  crossref Leo Raj Solay, Sunny Anand, S. Intekhab Amin, Pradeep Kumar 2022-02-03T20:30:23Z 置信度 0.70
• Flexible 256×256 All-Organic-Transistor Active-Matrix Optical Imager with Integrated Gate Driver
  crossref Weihong Yang, Jun Li, Peijin Huang, Simon Ogier 等 2026-01-30T21:00:04Z 置信度 0.70
• Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs
  crossref B. Iniguez, T.A. Fjeldly, A. Lazaro, F. Danneville 等 2006-08-23T15:36:32Z 置信度 0.70
• Negative Capacitance Gate-All-Around Nanowire FETs for Highly Sensitive Catalytic Metal Gate Gas Sensors
  crossref Nazmul Hasan Naime, Afsana Anjum Akhi, Mainul Hossain 2025-04-04T16:50:27Z 置信度 0.70
• Numerical Model of Gate-All-Around MOSFET With Vacuum Gate Dielectric for Biomolecule Detection
  crossref Rajni Gautam, Manoj Saxena, R. S. Gupta, Mridula Gupta 2012-09-19T14:12:14Z 置信度 0.70
• Impact of Interface Roughness on Threshold-Voltage Variation in Ultrasmall Gate-All-Around and Double-Gate Field-Effect Transistors
  Effects of interface roughness on the threshold-voltage variation of nanometer-size gate-all-around (GAA) and double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated using three-dimensional non-equilibrium Green's functio…
  crossref Nobuya Mori, Hideki Minari 2010-04-20T01:58:00Z 置信度 0.70
• Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET
  crossref Shaodi Wang, Xinjie Guo, Lining Zhang, Chenfei Zhang 等 2011-02-15T21:12:43Z 置信度 0.70
• High-K Spacer Gate Stack Engineered, Dual Metal Underlap Junction-less GaN Gate All Around (HKS-GSE-DMUL-JGaNGAA) MOSFET for High Frequency Applications
  crossref Anubha Goel, R. S. Gupta 2023-02-16T23:01:47Z 置信度 0.70
• Der IGBT (Insulated Gate Bipolar-Transistor)
  crossref Rainer Kassing 2018-04-13T05:52:02Z 置信度 0.70
• Umbrella-shaped gate field-effect transistor for biosensing measurements
  crossref Chengwu Tao 2018-08-10T15:38:27Z 置信度 0.70
• Environmentalists All Around Us
  crossref 2025-07-10T13:01:12Z 置信度 0.70
• Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs
  crossref X. Baie, J.P. Colinge 2002-07-25T13:28:40Z 置信度 0.70
• Impact of Interface-trapped Charges on the Performance of Gaussian-doped Gate-all-around Junctionless MOSFET
  crossref Princy Sharma, Subindu Kumar 2026-01-19T20:51:22Z 置信度 0.70
• Effects of the physical parameter on gate all around FET
  crossref Amit Agarwal, P C Pradhan, Bibhu P Swain 2019-12-03T08:03:24Z 置信度 0.70
• (Invited) Gate-All-Around Ge FETs
  High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced I on of 110 mA/mm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 m…
  crossref C. W. Liu, Yen-Ting Chen, Shu-Han Hsu 2014-09-30T16:56:20Z 置信度 0.70
• InAs nanowire gate-all-around MOSFETs by heterogeneous planar VLS growth
  crossref Chen Zhang, Wonsik Choi, Parsian Mohseni, Xiuling Li 2015-08-12T18:37:34Z 置信度 0.70
• Some Properties of SOI Gate-All-Around Devices
  crossref P. Francis, X. Baie, J. P. Colinge 2015-11-06T07:19:13Z 置信度 0.70
• Numerical Elucidation of the Electrothermal Characteristics of Gate-All-Around FET Devices
  crossref Faouzi Nasri, Husien Salama 2024-03-04T14:00:33Z 置信度 0.70
• Performance Enhancement in Uniaxially Tensile Strained-Si Gate-All-Around Nanowire n-MOSFETs
  crossref Pouya Hashemi, Leonardo Gomez, Michael Canonico, Judy L. Hoyt 2009-03-19T19:55:43Z 置信度 0.70
• Edge effects characterization in gate-all-around SOI MOSFETs
  crossref A. Vandooren, D. Flandre, S. Cristoloveanu, J.-P. Colinge 2002-11-27T17:03:01Z 置信度 0.70
• Compact Modelling of Quantum Confinement in III-V Gate All Around Nanowire MOSFET
  crossref Ahmed Abdelmoneam, Benjamin Iniguez, Mostafa Fedawy 2019-03-08T20:45:46Z 置信度 0.70
• Current-voltage model in depletion all around operation of InSb nanowire field effect transistor
  crossref Ifat Jahangir, Shafat Jahangir, Quazi D. M. Khosru 2010-12-23T18:01:26Z 置信度 0.70
• Process Flow Modelling and Characterisation of Stacked Gate-All-Around Nanosheet Transistors
  crossref K. Mumba, S. Cai, K. Kalna 2022-11-08T20:42:26Z 置信度 0.70
• A complete Verilog-A Gate-All-Around junctionless MOSFET model
  crossref Oana Moldovan, Francois Lime, Benjamin Iniguez 2016-01-21T18:13:43Z 置信度 0.70
• Silicon-on-insulator 'gate-all-around' MOS device
  crossref J.-P. Colinge, M.-H. Gao, A. Romano, H. Maes 等 2002-12-04T17:06:48Z 置信度 0.70
• Investigation of analog/RF performance of gate-all-around junctionless MOSFET including interfacial defects
  crossref H. Ferhati, F. Djeffal, T. Bentrcia 2016-02-25T21:20:47Z 置信度 0.70
• (Invited) Gate-All-Around Ge FETs
  Abstract - High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced I on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls and subthreshold characterist…
  crossref C. W. Liu, Yen-Ting Chen, Shu-Han Hsu 2020-02-27T00:51:01Z 置信度 0.70
• Modeling and analysis of gate-all-around silicon nanowire FET
  crossref Xiangchen Chen, Cher Ming Tan 2014-01-20T13:20:45Z 置信度 0.70
• Semi‐analytical modelling of short channel effects in Si double gate, tri‐gate and gate all‐around MOSFETs
  Abstract An analytical expression for the three‐dimensional potential distribution along the channel of short channel silicon multi‐gate MOSFETs is described in weak inversion. The analytical solutions cover three different cases of multi‐gate devices: Symmetr…
  crossref A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, G. Pananakakis 等 2008-09-16T16:50:08Z 置信度 0.70
• Planar Double-Gate Transistor
  crossref 2009-01-15T12:12:02Z 置信度 0.70
• Realization of Gate-All-Around (GAA) SOI MOSFET Using Replacement Gate Mask
  crossref A. L. Theng, W. L. Goh, Y. T. Chan, K. M. Tee 等 2008-02-15T15:15:11Z 置信度 0.70
• Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip.
  Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip. ................................................................................................................................................................................. اکنون «…
  datacite JALALI, SEYED RASOUL 2026 置信度 0.66
• Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip.
  Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip. ................................................................................................................................................................................. اکنون «…
  datacite JALALI, SEYED RASOUL 2026 置信度 0.66
• 3D VNWFET-Based Standard Cell Library
  The vertical nanowire field effect transistor (VNWFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, su…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.66
• 3D VNWFET-Based Standard Cell Library
  The vertical nanowire field effect transistor (VNWFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, su…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.66
• 3D VNWFET with Double Gate Stack (JL2) -Based Standard Cell Libraries
  Vertical Nanowire Field Effect Transistors (VNWFET) are emerging as a promising technology to overcome the scaling limitations of conventional lateral devices. The Junction-less (JL) device with a 3D gate-all-around (GAA) architecture offers several key advant…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.66
• 3D VNWFET with Double Gate Stack (JL2) -Based Standard Cell Libraries
  Vertical Nanowire Field Effect Transistors (VNWFET) are emerging as a promising technology to overcome the scaling limitations of conventional lateral devices. The Junction-less (JL) device with a 3D gate-all-around (GAA) architecture offers several key advant…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.66
• Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe: B Source/Drain
  We present an ultra-low-temperature (ULT) boron-doped SiGe (SiGe:B) epitaxial (epi) layer as PMOS junction in a gate-all-around (GAA) Si nanosheet (NS) transistor at 48 nm contacted poly-pitch (CPP) and 14 nm gate length (LG). We investigate the impact of dopa…
  datacite Sarkar, Ritam, Casey, Daniel, Dutta, Arka, Eyben, Pierre 等 2025 置信度 0.66
• Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe: B Source/Drain
  We present an ultra-low-temperature (ULT) boron-doped SiGe (SiGe:B) epitaxial (epi) layer as PMOS junction in a gate-all-around (GAA) Si nanosheet (NS) transistor at 48 nm contacted poly-pitch (CPP) and 14 nm gate length (LG). We investigate the impact of dopa…
  datacite Sarkar, Ritam, Casey, Daniel, Dutta, Arka, Eyben, Pierre 等 2025 置信度 0.66
• Gate-All-Around FET based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework
  Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses shortchannel effects by providing superior electrostatic control over the channel. Due to the …
  datacite Namgiri Snehith, Kanneganti Rohith Sai, Surala Deva Venkata Sai Anudeep, E Santosh Kumar 等 2023 置信度 0.66
• Gate-All-Around FET based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework
  Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses shortchannel effects by providing superior electrostatic control over the channel. Due to the …
  datacite Namgiri Snehith, Kanneganti Rohith Sai, Surala Deva Venkata Sai Anudeep, E Santosh Kumar 等 2023 置信度 0.66
• Density-Gradient Based Quantum Analysis of Nanowire Transistor
  The semiconductor devices scaling are changing very rapidly, which has triggered a non-conventional physical effect called quantum confinement. This dominant effect must need to be considered for submicron transistor modeling. The conventional drift–diffusion …
  datacite Andrew D. Adams, Satyendra N. Biswas 2026 置信度 0.66 Density-Gradient, quantum confinement, nanowire, electron concentration
• Density-Gradient Based Quantum Analysis of Nanowire Transistor
  The semiconductor devices scaling are changing very rapidly, which has triggered a non-conventional physical effect called quantum confinement. This dominant effect must need to be considered for submicron transistor modeling. The conventional drift–diffusion …
  datacite Andrew D. Adams, Satyendra N. Biswas 2026 置信度 0.66 Density-Gradient, quantum confinement, nanowire, electron concentration
• Electron-Electron Interactions in Device Simulation via Non-equilibrium Green's Functions and the GW Approximation
  The continuous scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) has led to device geometries where charged carriers are increasingly confined to ever smaller channel cross sections. This development is associated with reduced screening o…
  datacite Deuschle, Leonard, Cao, Jiang, Ziogas, Alexandros Nikolaos, Winka, Anders 等 2024 置信度 0.66 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Quantum Physics (quant-ph)FOS: Physical sciencesFOS: Physical sciences
• High frequency techniques for advanced MOS device characterization
  Rapid advances in the semiconductor industry have led to the proliferation of electric devices and information technology (IT). Integrated circuits(IC) based upon silicon MOSFET's have been used in virtually every electronic device produced today. The competit…
  datacite Wang, Yun 2008 置信度 0.66
• Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design
  In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design a static random-access memory (SRAM) using gate-all-around field-effect-transistor (GAA-FET) technology so that it is immune to single alpha part…
  datacite Lu, Albert, Arghavani, Reza, Wong, Hiu Yung 2025 置信度 0.66 Emerging Technologies (cs.ET)Computational Physics (physics.comp-ph)FOS: Computer and information sciencesFOS: Computer and information sciencesFOS: Physical sciences
• Channel-last gate-all-around nanosheet oxide semiconductor transistors
  As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gat…
  datacite Athena, Fabia F., Wu, Xiangjin, Safron, Nathaniel S., McKeown-Green, Amy Siobhan 等 2025 置信度 0.66 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Static Timing Analysis for Advanced Technology Nodes (5nm/3nm/2nm)
  Static Timing Analysis (STA) stands as a fundamental cornerstone of semiconductor design validation, evolving dramatically to meet the unprecedented challenges presented by advanced technology nodes. As transistor dimensions approach atomic scales at 5nm and b…
  datacite Naveen Kumar Siddappa Desai 2025 置信度 0.66
• Static Timing Analysis for Advanced Technology Nodes (5nm/3nm/2nm)
  Static Timing Analysis (STA) stands as a fundamental cornerstone of semiconductor design validation, evolving dramatically to meet the unprecedented challenges presented by advanced technology nodes. As transistor dimensions approach atomic scales at 5nm and b…
  datacite Naveen Kumar Siddappa Desai 2025 置信度 0.66
• EQPU – 0DSTL Architecture: Deterministic Quantum-Analog Computing Framework
  0DSTL Architecture Join the 0DSTL Architecture Community: A physically based, deterministic architecture built around 0DSTL.Researchers can submit prototypes, simulation results, implementation studies, and related computational models. For submissions or revi…
  datacite Torrisi, Sebastiano 2025 置信度 0.66 quantum computing, analog computation, deterministic logic, EQPU, 0DSTL
• EQPU – 0DSTL Architecture: Deterministic Quantum-Analog Computing Framework (v5)
  Update Notice – Version 5 Join the 0DSTL Architecture Community: A physically based, deterministic architecture built around 0DSTL.Researchers can submit prototypes, simulation results, implementation studies, and related computational models. For submissions …
  datacite Torrisi, Sebastiano 2025 置信度 0.66 quantum computing, analog computation, deterministic logic, EQPU, 0DSTLv5
• Performance and reliability potential of Bi$_2$O$_2$Se/Bi$_2$SeO$_5$ transistors
  While 2D materials have enormous potential for future device technologies, many challenges must be overcome before they can be deployed at an industrial scale. One of these challenges is identifying the right semiconductor/insulator combination that ensures hi…
  datacite Davoudi, Mohammad Rasool, Bahrami, Mina, Verdianu, Axel, Khakbaz, Pedram 等 2025 置信度 0.66 Materials Science (cond-mat.mtrl-sci)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Device-Scale Atomistic Simulations of Heat Transport in Advanced Field-Effect Transistors
  Self-heating in next-generation, high-power-density field-effect transistor limits performance and complicates fabrication. Here, we introduce NEP-FET, a machine-learned framework for device-scale heat transport simulations of field-effect transistors. Built u…
  datacite Xu, Ke, Wang, Gang, Liang, Ting, Xiao, Yang 等 2025 置信度 0.66 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Ion behavior near liquid/solid interface in nanowire FET biosensors
  This thesis investigates ion behavior at the liquid/solid interface in nanoscale silicon nanowire (Si NW) field-effect transistor (FET) biosensors. Advanced liquid gate-all-around (LGAA) NW FETs were developed to explore key interfacial effects, including char…
  datacite Zhang, Yongqiang 2025 置信度 0.66 Gate-all-aroundIon behaviorFETNoiseRandom telegraph signal
• Non-destructive lateral cavity etch measurements of 8-superlattice layer nanowire test structures using optical Mueller Matrix Spectroscopic Ellipsometry, X-Ray Diffraction and X-Ray Fluorescence
  The semiconductor industry is expected to move to sub 3 nm nodes of gate-all around CMOS (complementary metal oxide semiconductor) transistor structures in the near future. This scaling is enabled in part by utilizing increased numbers of Si/Si 1-x Ge x superl…
  datacite Schaefer, Mark, Kal, Subhadeep, Hetzer, Dave, Pasikatan, Ezra 等 2025 置信度 0.66 Physical sciencesFOS: Physical sciences