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• Advanced Verification Methodologies for Multi-Die Integrated Systems
  The semiconductor industry is experiencing a fundamental transformation as traditional monolithic system-on-chip integration encounters insurmountable economic and physical limitations at advanced process nodes. Escalating mask costs, yield degradation on larg…
  datacite Suri Babu Talla 2026 置信度 0.66
• Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems
  Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and performance, they also i…
  datacite Di Natale, Giorgio, Rabache, Christelle, Hellier, Pierre-Louis, Podevin, Florence 等 2026 置信度 0.66 Cryptography and Security (cs.CR)FOS: Computer and information sciencesFOS: Computer and information sciences
• Advancing 3DIC Technologies to Propel AI Innovations
  AI innovation has significantly boosted the demand for advanced packaging, particularly 3DIC solutions. These offer numerous benefits, including cost efficiency, design flexibility, and enhanced system performance. However, as AI product introduction accelerat…
  datacite IEEE International Symposium on Reliability Physics 2026, He, Jun 2026 置信度 0.66 Reliability Physics
• Insights into the Reliability of Advanced Glass Packages
  This talk explores the emergence of glass as a prime candidate for high-performance substrates in chiplet-based systems. Its unique mechanical properties allow for larger body sizes than traditional organic and silicon substrates; however, concerns about core …
  datacite Vanessa Smet 2024 置信度 0.66
• A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks
  Thermally aware design of 2.5D and 3D advanced packaging systems will require fast, accurate, and powerful thermal analysis of chiplets, stacks, and packages. These systems contain multiple materials with non-linear heat transfer properties and geometric featu…
  datacite Bloomfield, Max, Wasti, Amogh, Yang, Zongmin, Galarza, Matthew 等 2026 置信度 0.66 Other Computer Science (cs.OH)FOS: Computer and information sciencesFOS: Computer and information sciences
• STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
  Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional physical design for 2.5D heterogeneous systems typically prioritizes wirelength reduction through tight chiplet packing, thi…
  datacite Parekh, Varun Darshana, Hazenstab, Zachary Wyatt, Srinivasa, Srivatsa Rangachar, Chakrabarty, Krishnendu 等 2025 置信度 0.66 Hardware Architecture (cs.AR)Emerging Technologies (cs.ET)FOS: Computer and information sciences
• Design of Configurable and Extensible Accelerator Architecture for Machine Learning Algorithms
  Machine learning has gained a lot of attention over the past few years because of the wide range of applications it can be applied to. However, machine learning algorithms are typically computation-intensive and require hardware acceleration in order for them …
  datacite Liu, Chester 2020 置信度 0.66 Machine learning accelerator, sparse coding2.5D chiplet integration, heterogeneous integration, AIBElectrical EngineeringEngineering
• Design Techniques for Energy-Efficient and Scalable Machine Learning Accelerators
  Machine learning is a key application driver of new computing hardware. Designing high-performance machine learning hardware requires a large number of operations and a high memory bandwidth. The energy efficiency of the hardware is often limited by the data m…
  datacite Chou, Teyuh 2022 置信度 0.66 Machine learning acceleratorsElectrical EngineeringEngineering
• Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity
  The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conve…
  datacite Haque, Emad, Nalla, Pragnya Sudershan, Zhang, Jeff, Sapatnekar, Sachin S. 等 2025 置信度 0.66 Hardware Architecture (cs.AR)FOS: Computer and information sciencesFOS: Computer and information sciences
• Electrical and Thermal Performance Tuning of Spoof Plasmonic Interconnect
  This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for its superior thermal…
  datacite Yasmin, Rafichha, Jahan, Ishrat, Omar, Abdelrahman, Baten, Md. Zunaid 等 2025 置信度 0.66 Optics (physics.optics)Applied Physics (physics.app-ph)FOS: Physical sciencesFOS: Physical sciences
• ETP4HPC SRA6 White Paper – Hardware Components
  This is a white paper released as part of the ETP4HPC’s Strategic Research Agenda 6. Components for High-Performance Computing (HPC) face a range of new challenges driven by advancements in technology and emerging workloads, particularly in the context of Arti…
  datacite Duranton, Marc, Prunty, Craig 2025 置信度 0.66
• ETP4HPC SRA6 White Paper – Hardware Components
  This is a white paper released as part of the ETP4HPC’s Strategic Research Agenda 6. Components for High-Performance Computing (HPC) face a range of new challenges driven by advancements in technology and emerging workloads, particularly in the context of Arti…
  datacite Duranton, Marc, Prunty, Craig 2025 置信度 0.66
• Thermal Challenges and Opportunities: From Chip to Facility (video)
  Thermal management is becoming an ever more critical challenge for AI chips as the power density increases. Both chip-level and facility-level cooling solutions need to be developed and optimized in order to support the demand and needs. At the chip-level, adv…
  datacite Dr. Yin Hang 2024 置信度 0.66
• Thermal Challenges and Opportunities: From Chip to Facility (video)
  Thermal management is becoming an ever more critical challenge for AI chips as the power density increases. Both chip-level and facility-level cooling solutions need to be developed and optimized in order to support the demand and needs. At the chip-level, adv…
  datacite Dr. Yin Hang 2024 置信度 0.66
• SSCD Workshop on System, Circuit, Device, and Packaging Co-Optimization for Next Generation AI Systems
  Webinar Slides
  datacite Kunle Olukotun, Rio Yokota, Jinwook Oh, Pritish Narayanan 等 2024 置信度 0.66
• SSCD Workshop on System, Circuit, Device, and Packaging Co-Optimization for Next Generation AI Systems
  Webinar Video
  datacite Kunle Olukotun, Rio Yokota, Jinwook Oh, Pritish Narayanan 等 2024 置信度 0.66
• Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video)
  A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data - such as System-in-Package (SiP) and System-on-Chip (SoC) - is the absence of low-latency, high-bandwidth, and high-…
  datacite Tolga Tekin 2024 置信度 0.66
• Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video)
  A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data - such as System-in-Package (SiP) and System-on-Chip (SoC) - is the absence of low-latency, high-bandwidth, and high-…
  datacite Tolga Tekin 2024 置信度 0.66
• Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video)
  A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data - such as System-in-Package (SiP) and System-on-Chip (SoC) - is the absence of low-latency, high-bandwidth, and high-…
  datacite Tolga Tekin 2024 置信度 0.66
• Photonics Systems for High Performance – CPO, Towards Photonics Chiplets (Video)
  A major hurdle in developing next-generation systems for high-performance applications and industries that require handling large, secure data - such as System-in-Package (SiP) and System-on-Chip (SoC) - is the absence of low-latency, high-bandwidth, and high-…
  datacite Tolga Tekin 2024 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Slides
  MTT Webinar Slides
  datacite Kamal Samanta 2018 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Video
  MTT Webinar Video
  datacite Kamal Samanta 2018 置信度 0.66
• To Chiplet or Not To Chiplet: Heterogeneous Integration and Chiplets
  EPS Webinar
  datacite Mudasir Ahmad 2022 置信度 0.66
• Data Centers At Meta: Heterogeneous Integration Driven By AI/ML And Network Applications
  EPS Webinar
  datacite Ravi Agarwal 2022 置信度 0.66
• Chiplet-In-Wafer Technology For The Development Of III-V RF IC
  EPS Webinar
  datacite Florian Herrault 2021 置信度 0.66
• Recent Advances and Trends in Advanced Packaging
  EPS Webinar
  datacite John Lau 2022 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Slides
  MTT Webinar Slides
  datacite Kamal Samanta 2018 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Video
  MTT Webinar Video
  datacite Kamal Samanta 2018 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Video
  MTT Webinar Video
  datacite Kamal Samanta 2018 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Slides
  MTT Webinar Slides
  datacite Kamal Samanta 2018 置信度 0.66
• Millimeter Wave and 5G Multilayer 3D Integration and Packaging: Advanced Technologies and Techniques Video
  MTT Webinar Video
  datacite Kamal Samanta 2018 置信度 0.66
• SSCD Workshop on System, Circuit, Device, and Packaging Co-Optimization for Next Generation AI Systems
  Webinar Video
  datacite Kunle Olukotun, Rio Yokota, Jinwook Oh, Pritish Narayanan 等 2024 置信度 0.66
• SSCD Workshop on System, Circuit, Device, and Packaging Co-Optimization for Next Generation AI Systems
  Webinar Slides
  datacite Kunle Olukotun, Rio Yokota, Jinwook Oh, Pritish Narayanan 等 2024 置信度 0.66
• Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning
  Modern Artificial Intelligence (AI) workloads demand computing systems with large silicon area to sustain throughput and competitive performance. However, prohibitive manufacturing costs and yield limitations at advanced tech nodes and die-size reaching the re…
  datacite Mishty, Kaniz, Sadi, Mehdi 2024 置信度 0.66 Hardware Architecture (cs.AR)FOS: Computer and information sciencesFOS: Computer and information sciences
• Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
  Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been able to keep up with the dema…
  datacite Deric, Aleksa, Mitard, Kyle, Tajik, Shahin, Holcomb, Daniel 2024 置信度 0.66 Cryptography and Security (cs.CR)FOS: Computer and information sciencesFOS: Computer and information sciences
• Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Accelerators
  Advanced packaging offers a new design paradigm in the post-Moore era, where many small chiplets can be assembled into a large system. Based on heterogeneous integration, a chiplet-based accelerator can be highly specialized for a specific workload, demonstrat…
  datacite Hao, Xiaochen, Ding, Zijian, Yin, Jieming, Wang, Yuan 等 2023 置信度 0.66 Hardware Architecture (cs.AR)FOS: Computer and information sciencesFOS: Computer and information sciences
• ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
  Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an increase in embodied emissions, encompassing carbon emissions arising from design…
  datacite Sudarshan, Chetan Choppali, Matkar, Nikhil, Vrudhula, Sarma, Sapatnekar, Sachin S. 等 2023 置信度 0.66 Hardware Architecture (cs.AR)FOS: Computer and information sciencesFOS: Computer and information sciences
• Nanopackaging for AI , Power and THz Solutions
  EPS Webinar
  datacite Siddharth Ravichandran, Goutham Ezhilarasu, Kuan-Neng Chen 2023 置信度 0.66
• Floorplet: Performance-aware Floorplan Framework for Chiplet Integration
  A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs), chiplet-based architecture can reduce costs and increase reusability, representing a p…
  datacite Chen, Shixin, Li, Shanyi, Zhuang, Zhen, Zheng, Su 等 2023 置信度 0.66 Hardware Architecture (cs.AR)Emerging Technologies (cs.ET)FOS: Computer and information sciencesFOS: Computer and information sciences
• An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects
  In the wake of dwindling Moore's Law, to address the rapidly increasing complexity and cost of fabricating large-scale, monolithic systems-on-chip (SoCs), the industry has adopted dis-aggregation as a solution, wherein a large monolithic SoC is partitioned int…
  datacite Karempudi, Venkata Sai Praneeth, Bashir, Janibul, Thakkar, Ishan G 2023 置信度 0.66 Emerging Technologies (cs.ET)Applied Physics (physics.app-ph)Optics (physics.optics)FOS: Computer and information sciencesFOS: Physical sciences
• 3D Chiplet-Based Readout for Detectors
  crossref Adam Quinn 2024-02-15T04:47:00Z 置信度 0.70
• Maskless Lithography Optimized for Heterogeneous and Chiplet Integration
  crossref B. Matuskova, B. Povazay, R. Holly, F. Bogelsack 等 2021-03-18T16:03:58Z 置信度 0.70
• Chiplet Packaging and AI Defect Inspection
  crossref Himanandhan Reddy Kottur, Pratyush Shukla, Katayoon Yahyaei, Shiam Istiaq Firoz 等 2026-03-04T20:48:01Z 置信度 0.70
• Guest Editorial: 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part II
  crossref Qin-Fen Hao, Kuan-Neng Chen, Sandeep Kumar Goel, Hai Li 等 2025-12-23T18:31:23Z 置信度 0.70
• Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging^*
  crossref Partho Bhoumik, Christopher Bailey, Krishnendu Chakrabarty 2025-06-10T17:48:39Z 置信度 0.70
• Materials for Microelectronic Packaging
  crossref 2015-05-18T21:11:37Z 置信度 0.70
• Research on A Chiplet-based DSA (Domain-Specific Architectures) Scalable Convolutional Acceleration Architecture
  crossref Shiliang Zhu, Min Miao, Zhuanzhuan Zhang, Xiaolong Duan 2022-09-09T21:30:58Z 置信度 0.70
• Packaging TradeOffs and Decisions
  crossref 2010-02-04T21:10:39Z 置信度 0.70
• Fine-Pitch Die-to-Wafer Bonding Technologies for Chiplet Integration
  crossref Juliana Panchenko, Laura Wenzel, Steffen Bickel, Adil Shehzad 等 2025-11-10T18:45:25Z 置信度 0.70
• Microelectronics Packaging Materials and Applications
  crossref 2010-02-04T21:10:39Z 置信度 0.70
• Processing Technologies in Microelectronic Packaging
  crossref 2010-02-04T21:10:39Z 置信度 0.70
• Latest Molding Solutions for Increased size of the Advanced Package Size (2.xD/3D Chiplet)
  ABSTRACT In recent years, the demand for upscaling from wafer to panel level has increased as 2.5D/3D chiplets for generative AI(artificial intelligence) and HPC(high performance computing)are becoming larger and larger. To achieve increased I/O(input/output)c…
  crossref Tadashi Kubota 2025-12-01T20:27:08Z 置信度 0.70
• Radio Frequency and Microwave Packaging
  crossref 2015-05-18T21:11:37Z 置信度 0.70
• Micro Mushroom Plug and Receptacles for Reliable Chiplet Connection with Passive Alignment
  crossref Yoshio Mita, Ayako Mizushima, Noriko Kawai, Naonobu Shimamoto 2025-08-05T18:00:37Z 置信度 0.70
• Advanced semiconductor electronic packaging
  crossref 2025-06-05T05:32:46Z 置信度 0.70
• Chiplet Solution with FO-MCM Package in Edge and Cloud Computing (IMPACT 2023)
  crossref David Ho, Po Yuan James Su, Jacy Pu, Yu Po Wang 2023-12-22T19:18:28Z 置信度 0.70
• Introduction and Overview of Microelectronic Packaging
  crossref 2015-05-18T21:11:37Z 置信度 0.70
• Tier Transfer of Ultrathin Reconstituted- SiO₂ Chiplet Tiers
  crossref Ashita Victor, Muhannad S. Bakir 2025-01-08T20:18:37Z 置信度 0.70
• UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies
  crossref Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Wei-Chih Chen 等 2025-05-19T13:52:03Z 置信度 0.70
• Cost-Performance Co-Optimization for the Chiplet Era
  crossref Alexander Graening, Darayus Adil Patel, Giuliano Sisto, Erwan Lenormand 等 2025-03-11T17:30:44Z 置信度 0.70
• Current Status and Recent Trends in Chiplet Integration Technology
  crossref 2022-12-31T22:13:37Z 置信度 0.70
• Hybrid Substrates for Chiplet Design and Heterogeneous Integration Packaging
  crossref J. H. Lau, G. Chen, C. Yang, A. Peng 等 2023-01-23T20:03:43Z 置信度 0.70
• Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogeneous Chiplet Integration
  crossref Xiangyu Wang, Mihai Dragos Rotaru, Yu Haitao, Chai Tai Chong 等 2023-01-18T18:54:40Z 置信度 0.70
• Introduction and Overview of Microelectronics Packaging
  crossref 2010-02-04T21:10:39Z 置信度 0.70
• Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design
  crossref Fabian Schätzle, Carlos Falquez, Nam Ho, André Zambanini 等 2025-12-08T18:37:46Z 置信度 0.70
• The Simulation and Testing of UCIe Power Noise Based on Chiplet
  crossref Zhijun Long, Chenxi Yang, Jianguo Zhang, Bin Yu 等 2025-09-17T17:29:31Z 置信度 0.70
• AI BASED ADVANCED PHYSICAL DESIGN METHODOLOGIES FOR CHIPLET ARCHITECTURES ACROSS TECHNOLOGY NODES
  This paper proposed system integrates AI interactive visualization interface with advance PD methodology to address key challenges multiple technology nodes. The tools for AI timing violation heatmap generation, routing congestion analysis, AI macro PV, and po…
  crossref Mr Venkategowda 2026-08-07T18:00:26Z 置信度 0.70
• The Simulation and Testing of UCIe Power Noise Based on Chiplet
  crossref Zhijun Long, Chenxi Yang, Jianguo Zhang, Bin Yu 等 2026-06-10T19:59:01Z 置信度 0.70
• Uncertainty Quantification for Compressible Micro-Interconnects in Replaceable Integrated Chiplet Assembly Under Hypergravity
  Abstract The compressible micro-interconnects (CMIs) in replaceable integrated chiplet (PINCH) assemblies enable reusable integration in high-performance electronic devices. However, CMIs are sensitive to gravitational and inertial perturbations in the operati…
  crossref Liu Chu, Jiajia Shi, Eduardo Souza de Cursi 2025-10-11T15:45:03Z 置信度 0.70
• Optimizing Chiplet Placement in Thermally Aware Heterogeneous 2.5D Systems Using Reinforcement Learning
  crossref Partha Pratim Kundu, Zhuang Furen, Sezin Kircali Ata, Hou Yubo 等 2025-03-11T17:30:44Z 置信度 0.70
• Mainframe Packaging: The Thermal Conduction Module (TCM)
  crossref 2010-02-04T21:10:39Z 置信度 0.70
• Multi-Chiplet Implementation of a Replaceable Integrated Chiplet (PINCH) Assembly
  crossref Michael A. Nieves Calderon, Shane Oh, Jonathan R. Brescia, Muhannad S. Bakir 2024-02-06T14:10:11Z 置信度 0.70
• Design of Chiplet-based Domain-Specific Architecture Accelerator with Scalable Mac Array
  crossref Dongqing Fang, Zhensong Li, Bingjie Li, Wenbo Mu 等 2025-09-17T17:29:31Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2007-10-04T19:35:49Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2011-06-08T12:59:20Z 置信度 0.70
• A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
  crossref MD Arafat Kabir, Dusan Petranovic, Yarui Peng 2021-11-24T15:39:53Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2008-07-18T14:12:20Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2007-10-04T15:35:53Z 置信度 0.70
• chiplet, n.
  crossref 2023-07-20T22:00:31Z 置信度 0.70
• SIDDER: A Deep Reinforcement Learning Framework for Crosstalk-Aware Equalization in Chiplet Die-to-Die Interfaces
  crossref Hung Khac Le, SoYoung Kim 2026-07-09T19:44:03Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2006-11-16T03:32:42Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2007-10-04T19:35:53Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2007-10-04T15:35:52Z 置信度 0.70
• Packaging
  crossref 2017-04-06T23:33:30Z 置信度 0.70
• IEEE Transactions on Advanced Packaging publication information
  crossref 2008-07-18T18:29:19Z 置信度 0.70
• Optical Chiplet Using Membrane III-V Photonic Devices
  crossref S. Yamaoka, T. Hiraki, T. Minotani, Y. Shikama 等 2026-06-10T19:59:01Z 置信度 0.70
• Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
  crossref Vinicius C. Do Nascimento, Seunghyun Hwang, Michael J. Smith, Qiang Qiu 等 2024-11-21T19:03:18Z 置信度 0.70
• Design of Diamond Cooling Chip for Thermal Management of Chiplet-Based System
  crossref Jingyan Li, Jinfeng Chen, Penghui Guan, Qing Wang 等 2025-09-17T17:29:31Z 置信度 0.70
• Real-Time Effective Mechanical Property Characterization of Redistribution Layer (RDL) for Chiplet Integration
  crossref Dingjie Lu, Jun Liu, Wenzu Zhang, Richard Xian-Ke Gao 等 2026-02-24T20:55:10Z 置信度 0.70
• The Future of Electronics Packaging is Chiplet Architecture
  ABSTRACT The transition from monolithic System-on-Chip (SoC) designs to chiplet-based architectures has redefined the landscape of advanced electronics packaging, driven by demands for increased functionality, heterogeneous integration, and improved performanc…
  crossref Pavanbabu Arjunamahanthi, Himanandhan Reddy Kottur, Shajib Ghosh, Patrick Craig 等 2026-02-10T13:50:53Z 置信度 0.70
• High Speed Signal Design on Fan-Out RDL Interposer for Artificial Intelligence (AI) and Deep Neural Network (DNN) Chiplet Accelerators Application
  crossref Ming-Han Zhuang, Chih-Yuan Shih, Ho-Chuan Lin, Andrew Kang 等 2024-05-28T17:36:26Z 置信度 0.70
• Omelet: A Packaging-Aware Hierarchical Interconnect Simulator for 2.5D/3D Chiplet Architectures
  crossref Jiho Kim, Danish Baig, Faaiq Waqar, Ashita Victor 等 2026-08-04T19:09:02Z 置信度 0.70
• EUV-Patterned Diamond-Confined Metallic Hydrogen: A Lithographic Roadmap to Ambient-Condition Superconducting Hydrogen
  The recovery of metallic hydrogen at ambient temperature and pressure remains a grand challenge, largely because the kinetic barriers preventing the back-conversion to molecular H₂ are too small in the pure atomic phase. Here I propose a radically new approach…
  datacite Travaglini, Giustino 2026 置信度 0.66 Condensed matter physicsParticle physicsPhysical cosmologySolid-state physicsAtomic physics
• EUV-Patterned Diamond-Confined Metallic Hydrogen: A Lithographic Roadmap to Ambient-Condition Superconducting Hydrogen
  The recovery of metallic hydrogen at ambient temperature and pressure remains a grand challenge, largely because the kinetic barriers preventing the back-conversion to molecular H₂ are too small in the pure atomic phase. Here I propose a radically new approach…
  datacite Travaglini, Giustino 2026 置信度 0.66 Condensed matter physicsParticle physicsPhysical cosmologySolid-state physicsAtomic physics
• Ocaya-Yakuphanoğlu (OY) Analysis & Diode I-V Characterization
  This is an advanced, open-source Python tool for automated parameter extraction and series resistance (Rs) compensation in Metal-Oxide-Semiconductor (MOS) and Metal-Semiconductor (MS) Schottky devices. This repository implements the Ocaya-Yakuphanoğlu (OY) Met…
  datacite R.O. Ocaya 2026 置信度 0.66
• TCAD input decks and extraction scripts for "Ferroelectric Back-Gate Programming of Single- and Dual-Active-Layer a-IGZO TFTs: Screening-Limited Coupling and Trap-Mediated Window Collapse"
  Sentaurus Device (Synopsys W-2024.09-SP1) input decks, material parameter files, and Python extraction scripts supporting the above manuscript (submitted to Semiconductor Science and Technology, 2026). The dataset comprises: (i) calibration decks reproducing t…
  datacite Dargar, Shashi Kant, Dargar, Abha, Birla, Shilpi 2026 置信度 0.66 Electrical EngineeringDevice ModelingIII-V Compound Semiconductor Device Simulation
• Concepts and prototyping for scalable quantum computing based on conveyor-mode single-electron shuttling
  Universal quantum computing promises solutions to a wide range of problems of significant scientific and socioeconomic impact that are computationally intractable using classical hardware. Since physical qubits are inherently noisy and prone to decoherence, re…
  datacite Künne, Matthias 2026 置信度 0.66 Hochschulschriftphysics ; quantum computing ; quantum information ; semiconductor ; silicon ; GaAs ; quantum dot ; spin qubit ; quantum processor architecture ; scalability ; conveyor-mode shuttling
• "FPGA Device Architecture Dataset: Resource and Process Specifications for 766 Devices Across 145 Families and 14 Silicon Vendors"
  "This dataset catalogs architectural resource specifications for 766 field-programmable gate array (FPGA) devices spanning 145 device families, compiled from primary manufacturer datasheets and product selection guides. It covers every commercially significant…
  datacite Rushil Patel, P.Sumathi ., Saurav Kumar 2026 置信度 0.66
• Skalierbarer Qubit-Shuttle über Si/SiGe Quantenbus und T-junction : Leistungscharakterisierung von Heterostrukturen und Untersuchung elektrostatischer Potentialstörungen durch Elektronen-Shuttle
  The quest for the universal fault-tolerant quantum computing demands innovative solutions. The quantum error correction (QEC) emerges as a key point to demonstrate the fault-tolerate quantum computer regardless implementation platforms while requiring millions…
  datacite Xue, Ran 2026 置信度 0.66 conveyor-mode shuttling ; Si/SiGe quantum dots ; scalability ; shuttle tomography ; potential disorders
• NATS-Bench-MCU
  NATS-Bench-MCU: Hardware Measurements for NATS-Bench Topology Search Space on Nordic nRF5340 This dataset accompanies the paper "NATS-Bench-MCU: A Tabular Hardware Benchmark for Neural Architecture Search on Microcontrollers" (AutoML 2026). It provides direct,…
  datacite Zimmermann, Sebastian, Groh, René, Kist, Andreas M. 2026 置信度 0.66