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• Level 4 Autonomous Driving SoC, leveraging chiplet, advanced package and UCIe
  With the unprecedented growth of High-Performance Compute (HPC) and Autonomous Driving (AD) seen in recent times, the traditional chip design strategy is falling short and encountering a fundamental manufacturing limit. Smaller silicon dies, or “chiplets,” com…
  openalex Vinayak Agrawal, Francois Piednoel, Igor Elkanovich, Dwaipayan Sil 等 2023-08-01 置信度 0.72 Computer scienceInterconnectionInteroperabilityLeverage (statistics)Embedded system
• 3D Packaging for Heterogeneous Integration
  The next generation of competitive integrated high-performance devices demand increased device density, higher memory bandwidth, reduced global interconnects, increased energy efficiency, and a smaller footprint. Chiplet architecture is now recognized as funda…
  openalex Rahul Agarwal, Patrick Cheng, Priyal Shah, Brett Wilkerson 等 2022-05-01 置信度 0.72 Computer science
• Thermal Simulator for Advanced Packaging and Chiplet-Based Systems
  Heterogeneous chiplet-based integration is expected to provide performance scalability and cost-effectiveness for the next generation of microelectronic systems. Practical deployment of chiplet-based platforms, however, requires developing novel electronic des…
  openalex Yousef Safari, Adam Corbier, Dima Al Saleh, Fahad Rahman Amik 等 2025-03-11 置信度 0.72 Computer scienceThermalSimulationReliability engineeringEngineering
• Chiplet Design and Heterogeneous Integration Packaging
  ​The book focuses on the design, materials, process, fabrication, and reliability of chiplet design and heterogeneous integraton packaging.
  openalex John H. Lau 2023-01-01 置信度 0.72 Package designComputer scienceEngineering drawingEngineering
• Chiplet based approach for heterogeneous processing and packaging architectures
  Creating integrated systems on-chip (SoCs) for aerospace platforms is becoming increasingly intractable in advanced semiconductor nodes (<; 90 nm) due to: (1) the expense of semiconductor processing and fabrication, (2) sheer complexity in terms of number of c…
  openalex Gabriel Mounce, Jim Lyke, Stephen Horan, Wes Powell 等 2016-03-01 置信度 0.72 Computer science
• 11.1 AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems
  The AMD Instinct™ MI 300 Series accelerators were conceptualized to extract maximum HPC and AI capability from the latest silicon and advanced packaging technology, designed to operate as CPU hosted PCle® device, MI300X, as well as a self-hosted accelerated pr…
  openalex A.J. Smith, Eric Chapman, Chintan Patel, Raja Swaminathan 等 2024-02-18 置信度 0.72 Modular designClass (philosophy)Computer scienceSeries (stratigraphy)Computer architecture
• Recent Advances and Trends in Chiplet Design and Heterogeneous Integration Packaging
  Abstract In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost …
  openalex John H. Lau 2023-05-15 置信度 0.72 InterposerProcess integrationSystem in packageSystem integrationChip
• Extremely Large Area Integrated Circuit (ELAIC): An Advanced Packaging Solution for Chiplets
  The slow-down of Moore's-Law-related lithographic scaling in high-density semiconductor integrated circuits has created a major impact on the design of computing hardware architecture. Computer architects are exploring heterogeneous assemblies of specialized c…
  openalex Rabindra Nath Das, Jason J. Plant, Alex Wynn, Matthew Ricci 等 2023-05-01 置信度 0.72 Integrated circuit packagingComputer scienceElectronic packagingIntegrated circuitElectrical engineering
• The Energy-Efficient 10-Chiplet AI Hyperscale NPU on Large-Scale Advanced Package
  In this paper, we presented an AI hyperscale processing unit (HPU), integrating a pair of neural processing unit (NPU) and 8 high bandwidth memory (HBM) chiplets above a large scale advanced package, redistribution layer (RDL) interposer. We construct the adva…
  openalex Jiwon Yoon, Young-Su Kwon, Hyunwoo Kim, Juhyeon Lee 等 2024-05-28 置信度 0.72 InterposerComputer scienceChip-scale packagePower integrityThree-dimensional integrated circuit
• Advanced Packaging Using Chiplets and Standardized Physical Interfaces
  Electronic control units (ECU) for automotive and robotics are seen as one emerging technology driver for the chiplet technology. Such a system consists of several building blocks with dedicated functionality. Based on this wide range of functionalities, such …
  openalex Fabian Hopsch, Maudood Ahmed, Andy Heinig 2022-12-07 置信度 0.72 InteroperabilityNode (physics)Computer scienceAutomotive industryInterface (matter)
• ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
  Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to increased embodied emissions, arising from design, manufacturing, and packaging. Whi…
  openalex Chetan Choppali Sudarshan, Nikhil Matkar, Sarma Vrudhula, Sachin S. Sapatnekar 等 2024-03-02 置信度 0.72 Carbon footprintReuseComputer scienceSystem on a chipVery-large-scale integration
• Modeling and Analysis of Heterogeneously Integrated Chiplet-to-Chiplet Communication Link in 2.5D Advanced Packaging
  This study involves various routing layouts for chiplet-to-chiplet communication links based on the Bunch of Wires (BoW) standard, which are integrated within the 2.5D package. It encompasses multiple case studies examining single-layer and dual-layer routing …
  openalex Haofeng Sun, Bobi Shi, Thong Nguyen, José E. Schutt‐Ainé 等 2024-05-28 置信度 0.72 Link (geometry)Computer scienceComputer networkDistributed computing
• Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures
  We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects pro…
  openalex P. Coudrain, P. Chausse, L. Arnaud, Didier Lattard 等 2019-05-01 置信度 0.72 InterposerCharacterization (materials science)Computer scienceThrough-silicon viaProcess (computing)
• Die Embedding Challenges for EMIB Advanced Packaging Technology
  Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnects of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple …
  openalex Gang Duan, Yosuke Kanaoka, Robin McRee, Bai Nie 等 2021-06-01 置信度 0.72 InterconnectionDie (integrated circuit)DiceFlip chipChip
• Approach for Advanced Packaging for 2.5D/3D Chiplets
  This paper introduces a novel approach for processing advanced packages, e.g., 2.5D/3D devices, with compression molding MUF. With our unique molding structure, we are able to completely fill narrow gaps with resin without any entrapment voids. The proposed te…
  openalex T. Kubota, H. Oshida, S. Hayashiguchi, Yuichi Kajikawa 等 2024-04-17 置信度 0.72 Compression moldingCuring (chemistry)MoldTransfer moldingMaterials science
• The Next Era for Chiplet Innovation
  Moore's Law is slowing down and the associated costs are simultaneously increasing. These pressures have given rise to new approaches utilizing advanced packaging and integration such as chiplets, interposers, and$3\mathrm{D}$stacking. We first describe the ke…
  openalex Gabriel H. Loh, T. Raja Swaminathan 2023-04-01 置信度 0.72 Computer scienceProduct (mathematics)Variety (cybernetics)SoarStacking
• Integrated Design Ecosystem for Chiplets Heterogeneous Integration and Chip-to-Chip Interconnects in Advanced Packaging Technology
  As chiplets containing multiple diverse functional dies are integrated into a single package, the demand for advanced packages with higher density interconnects and larger footprint body sizes has surged. However, the inherent complexity and dense connectivity…
  openalex Lihong Cao, Chen-Chao Wang, Chih-Yi Huang, Hung‐Chun Kuo 2024-05-28 置信度 0.72 ChipSystem on a chipComputer scienceIntegrated circuit designChip-scale package
• A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets
  The Chiplet methodology can accelerate VLSI system development and provide better flexibility. However, it is not easy to build interconnection networks across multiple chiplets and maintain high-performance deadlock-free routing in systems of various hierarch…
  openalex Yinxiao Feng, Dong Xiang, Kaisheng Ma 2023-02-01 置信度 0.72 Computer scienceInterconnectionDistributed computingScalabilityNetwork topology
• Signal Integrity Simulation and Analysis for 2.5D Advanced Package Interconnect Based on Universal Chiplet Interconnect Express (UCIe)
  This paper presents the design and signal integrity (SI) simulation of 2.5D advanced packaging interconnects based on the Universal Chiplet Interconnect Express (UCIe) protocol. The study compares multiple interconnect structures, including silicon bridge, waf…
  openalex Yuxuan Fan, Hanchen Gan, Yunyan Zhou, Bo Lei 等 2024-12-03 置信度 0.72 Signal integrityInterconnectionComputer scienceSystem in packagePackage design
• Exploring Advanced Packaging Technologies for Reverse Engineering a System-in-Package (SiP)
  System-in-package (SiP) is a type of electronic packaging convention that integrates multiple components, such as microprocessors, memory, sensors, and so on, in the form of chiplets into a single unified package. SiP integration, enabled by advanced packaging…
  openalex M Shafkat M Khan, Chengjie Xi, Md Saad Ul Haque, Mark Tehranipoor 等 2023-09-01 置信度 0.72 System in packageExploitComputer sciencePackaging engineeringSupply chain
• Chiplet Heterogeneous Integration
  openalex John H. Lau 2021-01-01 置信度 0.72 System integrationComputer scienceSymmetric multiprocessor systemData integrationSystems engineering
• Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
  This work advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and joint simulation of signal and power integrity of BoW-based die-to-die interconnects with advanced packaging technology. The…
  openalex Ram Krishna, Atom O. Watanabe, John Golz, Ravi Bonam 等 2023-05-01 置信度 0.72 Signal integrityPower integrityInterface (matter)Electric power transmissionComputer science
• Scalable Advanced DBHi Chiplet Package Using Silicon Bridge With 30 µm-Pitch Solder Joints
  Direct-bonded heterogeneous integration (DBHi) is a unique chiplet packaging technology using directly-bonded silicon bridges as high-density inter-chip connections. In this paper, we present the reliability results of the DBHi packages on standard laminate su…
  openalex Akihiro Horibe, Takahito Watanabe, Chinami Marushima, Sayuri Kohara 等 2024-05-28 置信度 0.72 SolderingChip-scale packageBridge (graph theory)SiliconComputer science
• Advanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration
  The increasing amount of data from all sectors driven by digital transformation is raising a problem of operational and storing cost of the data. Meanwhile, the exponential cost leaps of silicon scaling, the unfordable increasing of Si die size over reticle li…
  openalex Lihong Cao 2023-12-13 置信度 0.72 EngineeringInterconnectionDie (integrated circuit)System in packageBottleneck
• Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages
  Organic interposer (CoWoS®-R) is one of the most promising heterogeneous integration platform solutions for high-speed and artificial intelligence applications. Components such as chiplets, high-bandwidth memory, and passives can be integrated into an organic …
  openalex Po-Yao Lin, M.C. Yew, Shu‐Shen Yeh, S. M. Chen 等 2021-06-01 置信度 0.72 InterposerBall grid arrayFlip chipReliability (semiconductor)Back end of line
• Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies
  The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to convert such flexibility into cost efficiency, which is critical when makin…
  openalex Tianqi Tang, Yuan Xie, Tang, Tianqi, Xie, Yuan 2022 置信度 0.72 Flexibility (engineering)Computer scienceGranularityInterconnectionPartition (number theory)
• Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration
  A chiplet is an integrated circuit (IC) that encompasses a well-defined subset of an overall systems functionality. In contrast to traditional monolithic system-on-chips (SoCs), chipletbased architecture can reduce costs and increase reusability, representing …
  openalex Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng 等 2023-12-28 置信度 0.72 FloorplanComputer scienceReusabilityComputer architectureArchitecture
• Advanced Package FAB Solutions(APFS) for Chiplet Integration
  For HPC applications, 2.5D and 3D technologies are employed for cloud, AI and ML. High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. This makes various solutions, such as M…
  openalex Seung Wook Yoon 2022-12-03 置信度 0.72 InterposerInterconnectionReticleComputer scienceNode (physics)
• Study of High-Density Optical Redistribution Layer Enabling Advanced Chiplet Edge Bandwidth Density on Active Optical Package Substrate
  Toward a next generation co-packaged optics, we have been developing a novel package substrate working as optoelectronic conversion engines and providing optical redistribution (ORDL) function and detachable optical connector. In this paper, we show its potent…
  openalex Akihiro Noriki, Fumi Nakamura, Satoshi Suda, Tadashi Murao 等 2025-05-27 置信度 0.72 OptoelectronicsMaterials scienceBandwidth (computing)Redistribution (election)Layer (electronics)
• CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package
  Chip-on-wafer-on-substrate (CoWoS®) is an advanced packaging technology to make high performance computing (HPC) and artificial intelligence (AI) components. As a high-end system-in-package (SiP) solution, it enabled multi-chip integration in a side-by-side ma…
  openalex Yuchen Hu, Yu-Min Liang, Hsieh-Pin Hu, Chia-Yen Tan 等 2023-05-01 置信度 0.72 InterposerSystem in packageChipComputer scienceEmbedded system
• Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration
  In recent electronic product market, high density chiplet package integration is taking leads to the world of "more than Moore". Since breaking down from a large chip, multi-chip architectures provide high performance and low cost of electronic production. The…
  openalex Teck-Chong Lee, Shuhan Yang, Hsin‐Yi Wu, You-Jun Lin 2022-05-01 置信度 0.72 Application-specific integrated circuitChipFlip chipIntegrated circuitWafer
• Application Defined On-chip Networks for Heterogeneous Chiplets: An Implementation Perspective
  With the help of advanced packaging technologies to integrate multiple chips (e.g., CPU, AI, IO), a chiplet-based SoC design process can enable fast system construction. However, the design of network-on-chip used within the individual chiplets and across chip…
  openalex Tianqi Wang, Feng Fan, Shaolin Xiang, Qi Li 等 2022-04-01 置信度 0.72 Computer scienceEmbedded systemComputer architectureKey (lock)Process (computing)
• Driving Compute Scale-out Performance with Optical I/O Chiplets in Advanced System-in-Package Platforms
  openalex Mark T. Wade, Chen Sun, Matt Sysak, Vladimir Stojanović 等 2023-08-27 置信度 0.72 Computer scienceScale (ratio)Embedded systemComputational sciencePhysics
• Warpage and RDL Stress Analysis in Large Fan-Out Package with Multi-Chiplet Integration
  As the advanced packaging technology is required to fulfill digitalized industry with big data, such as high performance computing (HPC), data center server, router, and switcher applications. Due to the hunger from above market needs, great interests were ind…
  openalex Jen-Hsien Wong, Nan-Yi Wu, Wei‐Hong Lai, Dao-Long Chen 等 2022-05-01 置信度 0.72 Power integrityTRACE (psycholinguistics)Computer scienceChipReliability (semiconductor)
• Advanced Packaging Solutions by Intergrating 2.5D/3D Chiplet, Wafer Panel Level Package
  This paper introduces an approach to panel level package (PLP) molding to meet the demand for an effective large-format packaging technology. For PLP molding, compression molding is an effective molding method that forms a package by compressing thermosetting …
  openalex K. Izusawa, S. Teramoto, Yuichi Kajikawa, S. Hayashiguchi 等 2025-04-15 置信度 0.72 WaferWafer-level packagingElectronic packagingWafer-scale integrationChip-scale package
• Multi-Package Co-Design for Chiplet Integration
  Due to the cost and design complexity associated with advanced technology nodes, it is difficult for traditional monolithic System-on-Chip to follow the Moore's Law, which means the economic benefits have been weakened. Semiconductor industries are looking for…
  openalex Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho 2022-10-30 置信度 0.72 Computer scienceReliability (semiconductor)Package on packageInterconnectionReliability engineering
• 3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators
  Exponential growth in the number of parameters used to train deep neural network (DNN)/machine learning (ML) models for artificial intelligence (AI) training/ inference applications requires extensive compute resources like CPUs, GPUs, and memory, interconnect…
  openalex Chandra Sekhar Mandalapu, Chintan Buch, Priyal Shah, Roden Topacio 等 2024-05-28 置信度 0.72 Computer scienceComputer architectureSystems engineeringEmbedded systemEngineering
• A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System
  Due to a variety of limitations on the system-on-chip (SoC), the microelectronics industry is now facing challenges and making slow progress in recent years. With architecture design and advanced packaging advantages, chiplet heterogeneous integration (CHI) sy…
  openalex Chenghan Wang, Qinzhi Xu, Chuanjun Nie, He Cao 等 2023-10-18 置信度 0.72 Thermal conductivityMicroelectronicsComputer scienceThermalIsotropy
• Chiplet-Gym: Optimizing Chiplet-Based AI Accelerator Design With Reinforcement Learning
  Modern Artificial Intelligence (AI) workloads demand computing systems with large silicon area to sustain throughput and competitive performance. However, prohibitive manufacturing costs and yield limitations at advanced tech nodes and die-size reaching the re…
  openalex Kaniz Mishty, Mehdi Sadi 2024-09-11 置信度 0.72 Reinforcement learningComputer scienceComputer architectureArtificial intelligence
• Review of chiplet-based design: system architecture and interconnection
  openalex Yafei Liu, Xiangyu Li, Shouyi Yin 2024-07-19 置信度 0.72 InterconnectionComputer architectureArchitectureComputer scienceComputer network
• From 2.5D to 3D Chiplet Systems: Investigation of Thermal Implications with HotSpot 7.0
  Recent advanced packaging technologies such as 2.5D chiplet-package offer a modular approach to increasing yield over monolithic SoC designs. As 2.5D chiplet systems shed light on reducing product development times and costs, 3D chiplet systems can extend the …
  openalex Jun-Han Han, Xinfei Guo, Kevin Skadron, Mircea R. Stan 2022-05-31 置信度 0.72 Modular designMicrofluidicsThermal management of electronic devices and systemsHotspot (geology)Thermal
• Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration
  Integrating heterogeneous chiplets in a package presents a promising and cost-effective approach to constructing scalable and flexible systems for accelerating a wide range of workloads. We introduce Arvon that integrates a 14-nm FPGA chiplet with two efficien…
  openalex Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer 等 2023-12-27 置信度 0.72 Field-programmable gate arrayAdapter (computing)Computer scienceDigital signal processingLatency (audio)
• Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond
  This article reviews current research and development as well as future opportunities for packaging and antenna integration technologies for silicon-based millimeter-wave phased arrays in emerging communication applications. Implementations of state-of-the-art…
  openalex Xiaoxiong Gu, Duixian Liu, Bodhisatwa Sadhu 2021-01-01 置信度 0.72 Phased arrayAntenna (radio)InterconnectionExtremely high frequencyEmphasis (telecommunications)
• Enabling AI Revolution Through Innovations in Advanced Packaging &amp; Chiplet Technology
  Chiplet architectures and advanced packaging, spearheaded by 3.5D integration in AMD's MI300x, have become paramount for sustaining power-efficient growth in AI and edge computing. As Moore's Law slows, these technologies push the envelope of performance, offe…
  openalex Raja Swaminathan 2024-04-22 置信度 0.72 Modularity (biology)Computer scienceArchitectureSystems engineeringEnhanced Data Rates for GSM Evolution
• Testing Inter-Chiplet Communication Interconnects in a Disaggregated SoC Design
  The integration of High-bandwidth memory (HBM), is essentially one of the first proof points of in-package integration of heterogeneous silicon that gained steam using advanced packaging. Intel has demonstrated heterogenous integration through chiplet architec…
  openalex Salem Abdennadher 2021-06-07 置信度 0.72 InterconnectionComputer scienceComputer architectureEmbedded systemIntegrated circuit design
• Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration
  The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to overcome the slowdown in Moore’s Law and Dennard scaling and to respond to the i…
  openalex Md Sami Ul Islam Sami, Tao Zhang, Amit Mazumder Shuvo, Md Saad Ul Haque 等 2024-01-01 置信度 0.72 Computer scienceHardware security moduleRobustness (evolution)Modular designEmbedded system
• System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration
  A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency,…
  openalex Ming-Fa Chen, Fang-Cheng Chen, Wen-Chih Chiou, Doug C. H. Yu 2019-05-01 置信度 0.72 InterposerThree-dimensional integrated circuitSystem in packagePower integrityScalability
• Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design
  With the increasing popularity and applications of 2.5-D integration, both chip and packaging industries are making significant progress in this direction. In advanced high-density 2.5-D packages, package redistribution layers become similar to chiplet back-en…
  openalex MD Arafat Kabir, Yarui Peng 2021-03-30 置信度 0.72 Agile software developmentDesign flowComputer scienceEmbedded systemParasitic extraction
• Latest Molding Solutions for Increased Size of the Advanced Package Size (2.xD/3D Chiplet)
  In recent years, the demand for upscaling from wafer to panel level has increased as 2.5D/3D chiplets for generative AI(artificial intelligence) and HPC(high performance computing)are becoming larger and larger. To achieve increased I/O (input/output) counts, …
  openalex Tadashi Kubota 2025-01-27 置信度 0.72 Molding (decorative)Computer scienceMaterials scienceEngineering drawingEngineering
• Stress and Fatigue Life Studies of Solder Joints in an Advanced Packaging with Chiplet
  Aiming at the structural reliability problem in the 3D packaging structure of Chiplet with TSV (Through Silicon Via), combined with finite element analysis, the stress, fatigue life of the solder joints, and the deformation degree of the TSV are predicted unde…
  openalex Kaiyuan Liu, Houyun Qin, Jiarui Guo, Yi Zhao 2023-06-01 置信度 0.72 SolderingDeformation (meteorology)Stress (linguistics)Materials scienceEnhanced Data Rates for GSM Evolution
• Proposed Standardization of Heterogenous Integrated Chiplet Models
  With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions…
  openalex Anthony Mastroianni, Benjamin Kerr, Jawad Nasrullah, Kevin Cameron 等 2021-10-01 置信度 0.72 StandardizationComputer scienceOperating system
• Two-Dimensional Thermal-Induced Warpage Prediction for Multi-Chiplet Heterogeneous Integration System in Advanced Packaging
  Thermal-induced warpage is a bottleneck problem in advanced packaging technology. In this paper, a new way of predicting the warpage deformation is proposed for multi-chiplet heterogeneous integration system, where the system deformations are considered as the…
  openalex He Cao, Qinzhi Xu, Jianyun Liu, Zhiqiang Li 等 2025-04-18 置信度 0.72 Materials scienceThermalElectronic packagingIntegrated circuit packagingComputer science
• Advanced Fanout Packaging Technology for Hybrid Substrate Integration
  Advanced packaging technologies such as 2.5D Si TSV interposer, Fanout RDL interposer and 3D hybrid bonding packaging have been developed for chiplets and system heterogeneous integrations to fulfil the continuous pursuit of higher performance, higher bandwidt…
  openalex Lihong Cao, Teck Chong Lee, Rick Chen, Yung-Shun Chang 等 2022-05-01 置信度 0.72 Ball grid arrayInterposerSystem in packageChipElectronic engineering
• Enabling scalable chiplet-based uniform memory architectures with silicon photonics
  Chiplet-based systems have recently received much attention for scaling-up processing power in HPC systems due to their high energy efficiency and low cost manufacturing; however, large inter-chiplet NUMA latencies, distance-related energy overheads, and limit…
  openalex Pouya Fotouhi, Sebastian Werner, Jason Lowe-Power, Sung Jong Yoo 2019-09-30 置信度 0.72 ScalabilityComputer scienceInterconnectionStatic random-access memoryBandwidth (computing)
• A Polymer-Based Embedded Silicon Fan-Out Packaging (P-eSiFO) Method for High-Density Chiplet Packaging
  Embedded silicon fan-out packaging (eSiFO) features excellent electrical and thermal performances as well as scalability to 3-D packaging and heterogeneous integration, making it a promising packaging technology for chiplet integration. Nevertheless, conventio…
  openalex Lang Chen, Bo Wen, Jianyu Du, Jinwen Zhang 等 2023-10-02 置信度 0.72 SiliconMaterials scienceElectronic packagingIntegrated circuit packagingPolymer
• Chiplets Integrated Solution with FO-EB Package in HPC and Networking Application
  Since its introduction in the 1960s, high performance computing (HPC) has made enormous contribution to scientific, engineering and industrial competitiveness as well as other goverment missions. High data rate with high speed transmission has been required fo…
  openalex Po Yuan James Su, David Ho, Jacy Pu, Yu Po Wang 2022-05-01 置信度 0.72 SupercomputerComputer sciencePackage on packageDie (integrated circuit)Fan-out
• Chips, Dies, Chiplets and Dielets and Heterogeneous Integration
  Packaging is undergoing a major paradigm shift and promises to take up the lag caused by the slowing down of CMOS scaling. In this paper, we examine these shifts that have been driven by the scaling of key packaging metrics such as bump pitch, trace pitch, int…
  openalex Subramanian S. Iyer 2022-03-06 置信度 0.72 CMOSComputer scienceDie (integrated circuit)ScalingChip-scale package
• High Thermal Conductivity AlN Films for Advanced 3D Chiplets
  A novel “Cool 3D chiplet” concept is proposed, showcasing remarkable heat dissipation through the integration of aluminum nitride (AlN), an insulating material with high thermal conductivity. We conducted simulations analyzing the thermal impact of AlN as an i…
  openalex T. Takagi, Takeki Ninomiya, Masako Niwa, Shin’ya OBARA 等 2024-06-16 置信度 0.72 Thermal conductivityMaterials scienceThermalConductivityOptoelectronics
• Advanced Chiplet Placement and Routing Optimization Considering Signal Integrity
  This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integrity-aware hierarchical Markov…
  openalex Haeyeon Kim, Junghyun Lee, Seonguk Choi, Federico Berto 等 2025-04-15 置信度 0.72 Signal integrityComputer sciencePlacementRouting (electronic design automation)Electronic engineering
• State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding
  Abstract In this study, the recent advances and trends of chip-let design and heterogeneous integration packaging will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, lateral interconnects, and examples of chiplet de…
  openalex John H. Lau 2021-10-01 置信度 0.72 Emphasis (telecommunications)Integrated circuit packagingEngineeringWire bondingSolid-state
• Big-Little Chiplets for In-Memory Acceleration of DNNs
  Monolithic in-memory computing (IMC) architectures face significant yield and fabrication cost challenges as the complexity of DNNs increases. Chiplet-based IMCs that integrate multiple dies with advanced 2.5D/3D packaging offers a low-cost and scalable soluti…
  openalex Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang 等 2022-10-30 置信度 0.72 Computer scienceScalabilityInterconnectionDramBandwidth (computing)
• Design and Analysis of an APU for Exascale Computing
  The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability, and cost. This paper presents a vision for an architecture that can be used to construct exascale syste…
  openalex Thiruvengadam Vijayaraghavan, Arun Karunanithi, Onur Kayıran, Mitesh R. Meswani 等 2017-02-01 置信度 0.72 Computer scienceExascale computingSupercomputerMemory bandwidthComputer architecture
• Performance and Reliability of Advanced CW Lasers for Silicon Photonics Applications
  Co-Packaged Optics (CPO) using Silicon Photonics Chiplets in Package (SCIP) is an essential technology for flattening the power consumption curve for Networking and Compute applications in Hyperscale Datacenters. CW lasers are integral to the operation of thes…
  openalex John E. Johnson, K. Bacher, Rebecca K. Schaevitz, Vivek Raghunathan 2022-01-01 置信度 0.72 PhotonicsReliability (semiconductor)Silicon photonicsFlatteningLaser
• NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging
  NetFlex is a multi-chiplet package (MCP) for CNN-based perception acceleration. With a balanced parallelism for mapping and a flexible scheduling, the NetFlex chiplet supports convolution, deconvolution and fully connected layers of different shapes, sizes and…
  openalex Teyuh Chou, Wei Tang, Mihai Rotaru, Chester Liu 等 2022-06-12 置信度 0.72 WaferDeconvolutionConvolution (computer science)Computer scienceInterface (matter)
• MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
  Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach their limits. 2.5D/3D heterogeneous integration of smaller chiplets using advanced p…
  openalex Lukas Pfromm, Alish Kanani, Harsh Sharma, Parth Solanki 等 2025-09-04 置信度 0.72 Computer scienceFidelityTelecommunications
• Automated Design of Chiplets
  Chiplet-based designs have gained recognition as a promising alternative to monolithic SoCs due to their lower manufacturing costs, improved re-usability, and optimized technology specialization. Despite progress made in various related domains, the design of …
  openalex Alberto Sangiovanni‐Vincentelli, Zheng Liang, Zhe Zhou, Jiaxi Zhang 2023-03-22 置信度 0.72 UsabilityComputer scienceTask (project management)Software engineeringSystems engineering
• Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part I
  openalex Qinfen Hao, Kuan‐Neng Chen, Sandeep Goel, Hai Li 等 2025-09-01 置信度 0.72 Electronic circuitElectrical engineeringEngineeringComputer scienceIntegrated circuit
• Near-sensor and in-sensor computing
  openalex Feichi Zhou, Yang Chai 2020-11-17 置信度 0.72 Computer scienceWireless sensor networkProcess (computing)ComputationData processing
• Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling
  Since the invention of the transistor, we have enjoyed tremendous impact of semiconductors on electronic systems. Transistor scaling has played a critical role in achieving increased functionality of semiconductor systems in main-frames, personal computers, an…
  openalex Surya Bhattacharya, Vempati Srinivasa Rao 2023-06-11 置信度 0.72 ToolboxScalingTransistorComputer scienceSystem integration
• Reliability Challenges of High-Density Fan-out Packaging for High-Performance Computing Applications
  As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach…
  openalex Laurene Yip, Rosa Lin, Charles Pin‐Kuang Lai, Cooper Peng 2022-05-01 置信度 0.72 Fan-outChip-scale packageInterconnectionReliability (semiconductor)Integrated circuit packaging
• System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning
  With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of system and package-level co-design methods make it difficult for…
  openalex Kaniz Mishty, Mehdi Sadi 2023-05-31 置信度 0.72 Bayesian optimizationComputer scienceDesign space explorationMathematical optimizationFunction (biology)
• Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators
  Advanced packaging offers a new design paradigm in the post-Moore era, where many small chiplets can be assembled into a large system. Based on heterogeneous integration, a chiplet-based accelerator can be highly specialized for a specific workload, demonstrat…
  openalex Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang 等 2023-10-28 置信度 0.72 Computer scienceLeverage (statistics)DataflowMonad (category theory)Workload
• Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity
  The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conve…
  arxiv Emad Haque, Pragnya Sudershan Nalla, Jeff Zhang, Sachin S. Sapatnekar 等 2025-11-13T19:29:35Z 置信度 0.78 cs.AR
• The application of collagen in advanced wound dressings
  Chronic wounds fail to proceed through an orderly and timely self healing process, resulting in cutaneous damage with full thickness in depth and leading to a major healthcare and economic burden worldwide. In the UK alone, 200,000 patients suffer from a chron…
  arxiv Giuseppe Tronci 2018-04-24T20:54:36Z 置信度 0.78 q-bio.TO
• Machine-learning based methodologies for 3d x-ray measurement, characterization and optimization for buried structures in advanced ic packages
  For over 40 years lithographic silicon scaling has driven circuit integration and performance improvement in the semiconductor industry. As silicon scaling slows down, the industry is increasingly dependent on IC package technologies to contribute to further c…
  arxiv Ramanpreet S Pahwa, Soon Wee Ho, Ren Qin, Richard Chang 等 2021-03-08T15:44:18Z 置信度 0.78 cs.CV
• The Survey of Chiplet-based Integrated Architecture: An EDA perspective
  Enhancing performance while reducing costs is the fundamental design philosophy of integrated circuits (ICs). With advancements in packaging technology, interposer-based chiplet architecture has emerged as a promising solution. Chiplet integration, often refer…
  arxiv Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai 等 2024-11-07T03:58:46Z 置信度 0.78 cs.AR
• Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
  Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP faces manufacturing challenges such as coefficient of thermal expa…
  arxiv Partho Bhoumik, Christopher Bailey, Krishnendu Chakrabarty 2025-03-18T23:23:45Z 置信度 0.78 eess.SY
• From Compact Plasma Particle Sources to Advanced Accelerators with Modeling at Exascale
  Developing complex, reliable advanced accelerators requires a coordinated, extensible, and comprehensive approach in modeling, from source to the end of beam lifetime. We present highlights in Exascale Computing to scale accelerator modeling software to the re…
  arxiv Axel Huebl, Remi Lehe, Edoardo Zoni, Olga Shapoval 等 2023-03-22T19:18:17Z 置信度 0.78 physics.acc-phcs.SEphysics.plasm-ph
• Hecaton: Training Large Language Models with Scalable Chiplet Systems
  Large Language Models (LLMs) have achieved remarkable success in various fields, but their training and finetuning require massive computation and memory, necessitating parallelism which introduces heavy communication overheads. Driven by advances in packaging…
  arxiv Zongle Huang, Shupei Fan, Chen Tang, Xinyuan Lin 等 2024-07-08T09:47:35Z 置信度 0.78 cs.AR
• HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
  2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects (ICIs). As the number of chiplets grows to tens or hun…
  arxiv Patrick Iff, Maciej Besta, Matheus Cavalcante, Tim Fischer 等 2022-11-25T09:54:02Z 置信度 0.78 cs.ARcs.DCcs.NI
• Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more…
  arxiv Jingwei Cai, Zuotong Wu, Sen Peng, Yuchen Wei 等 2023-12-27T06:45:06Z 置信度 0.78 cs.AR
• Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems
  Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and performance, they also i…
  arxiv Giorgio Di Natale, Christelle Rabache, Pierre-Louis Hellier, Florence Podevin 等 2026-05-08T09:27:24Z 置信度 0.78 cs.CR
• CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration
  Advanced 2.5D Systems-in-Package (SiPs) compose a growing portion of high-performance systems. While the packaging and interconnect choices play a large role in the overall system design, system architects still lack a suitable framework for early design space…
  arxiv Zhengping Zhu, Austin Rovinski 2026-05-26T23:13:32Z 置信度 0.78 cs.AR
• Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
  Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous computing with domain-specific architectures (DSAs) brings many opportunities whe…
  arxiv Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang 等 2023-11-28T01:50:09Z 置信度 0.78 cs.AR
• Advanced Drone Swarm Security by Using Blockchain Governance Game
  This research contributes to the security design of an advanced smart drone swarm network based on a variant of the Blockchain Governance Game (BGG), which is the theoretical game model to predict the moments of security actions before attacks, and the Strateg…
  arxiv Song-Kyoo Kim 2021-12-29T18:05:46Z 置信度 0.78 eess.SYcs.CRcs.GT
• Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices
  The memristor can be used as non volatile memory (NVM) and for emulating neuron behavior. It has the ability to switch between low resistance $R_{on}$ and high resistance values $R_{off}$, and exhibit the synaptic dynamic behaviour such as potentiation and dep…
  arxiv Aidana Irmanova, Grant A. Ellis, Alex Pappachen James 2018-09-27T10:01:33Z 置信度 0.78 cs.ET
• Package-Embedded Coupled Inductor Arrays for High-Performance Computing Power Delivery
  A novel power delivery framework, comprising a package-embedded inductor topology and an inductance-island methodology, is introduced to maximize both inductance and current densities in vertical power delivery (VPD). The framework leverages multiple multi-pha…
  arxiv Rami Rasheedi, Salma Abdelzaher, Inna Partin-Vaisband 2026-06-01T20:47:21Z 置信度 0.78 eess.SY
• Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles
  On the advent of the slow death of Moore's law, the silicon industry is moving towards a new era of chiplets. The automotive industry is experiencing a profound transformation towards software-defined vehicles, fueled by the surging demand for automotive compu…
  arxiv Swathi Narashiman, Venkat A, Divyaratna Joshi, Deepak Sridhar 等 2024-05-31T20:18:35Z 置信度 0.78 cs.AR
• Fast Thermal-Aware Chiplet Placement Assisted by Surrogate
  With the advent of the post-Moore era, the 2.5-D advanced package is a promising solution to sustain the development of very large-scale integrated circuits. However, the thermal placement of chiplet, due to the high complexity of thermal simulation, is very c…
  arxiv Qinqin Zhang, Xiaoyu Liang, Ning Xu, Yu Chen 2025-04-04T11:04:41Z 置信度 0.78 cs.OH
• RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
  Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge as there are many degrees of free…
  arxiv Patrick Iff, Benigna Bruggmann, Blaise Morel, Maciej Besta 等 2023-11-10T14:26:57Z 置信度 0.78 cs.AR
• Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures
  As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of monolithic chips. However, this transition int…
  arxiv Peter Wegmann, Aleksandra Świerkowska, Emmanouil Giortamis, Pramod Bhatotia 2026-03-17T11:20:37Z 置信度 0.78 quant-ph
• Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim
  This paper focuses on the simulation of multi-die System-on-Chip (SoC) architectures using VisualSim, emphasizing chiplet-based system modeling and performance analysis. Chiplet technology presents a promising alternative to traditional monolithic chips, which…
  arxiv Wajid Ali, Ayaz Akram, Deepak Shankar 2025-11-03T05:33:28Z 置信度 0.78 cs.ARcs.PF
• Package Hermeticity Testing with Thermal Transient Measurements
  The rapid incursion of new technologies such as MEMS and smart sensor device manufacturing requires new tailor-made packaging designs. In many applications these devices are exposed to humid environments. Since the penetration of moisture into the package may …
  arxiv Andras Vass-Varnai, M. Rencz 2008-05-07T09:52:00Z 置信度 0.78 cs.OH
• Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
  Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. I…
  arxiv Yinxiao Feng, Kaisheng Ma 2022-03-23T08:30:30Z 置信度 0.78 cs.AR
• Hardware Design and Security in the Era of Chiplets and LLMs
  The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefit…
  arxiv Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz, Ramesh Karri 2026-08-05T17:09:13Z 置信度 0.78 cs.CRcs.AIcs.AR
• Chiplets and the Codelet Model
  Recently, hardware technology has rapidly evolved pertaining to domain-specific applications/architectures. Soon, processors may be composed of a large collection of vendor-independent IP specialized for application-specific algorithms, resulting in extreme he…
  arxiv Dawson Fox, Jose M Monsalve Diaz, Xiaoming Li 2022-09-13T15:33:39Z 置信度 0.78 cs.DC
• Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation
  Chiplet-based systems, integrating various silicon dies manufactured at different integrated circuit technology nodes on a carrier interposer, have garnered significant attention in recent years due to their cost-effectiveness and competitive performance. The …
  arxiv Zhihui Deng, Yuanyuan Duan, Leilai Shao, Xiaolei Zhu 2024-04-07T12:40:37Z 置信度 0.78 cs.LGcs.AIcs.AR
• Novel Bonding technologies for wafer-level transparent packaging of MOEMS
  Depending on the type of Micro-Electro-Mechanical System (MEMS), packaging costs are contributing up to 80% of the total device cost. Each MEMS device category, its function and operational environment will individually dictate the packaging requirement. Due t…
  arxiv H. Kirchberger, P. Lindler, M. Wimpliger 2008-02-21T13:45:48Z 置信度 0.78 cs.OH
• Chiplet-Based RISC-V SoC with Modular AI Acceleration
  Achieving high performance, energy efficiency, and cost-effectiveness while maintaining architectural flexibility is a critical challenge in the development and deployment of edge AI devices. Monolithic SoC designs struggle with this complex balance mainly due…
  arxiv Suhas Suresh Bharadwaj, Prerana Ramkumar 2025-09-22T19:31:58Z 置信度 0.78 cs.ARcs.AI
• Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems
  In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical pa…
  arxiv J. Iannacci, Jason Tian, S. Sinaga, R. Gaddi 等 2007-11-21T08:24:39Z 置信度 0.78 cs.OH