半导体与先进封装 · 全部实体（第 8 / 100 页）

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• High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime
  crossref Yumei Yang, Haijun Lou, Xinnan Lin 2018-10-17T19:47:46Z 置信度 0.63
• Novel Gate-All-Around High-Voltage Thin-Film Transistor With T-Shaped Metal Field Plate Design
  crossref Jhen-Yu Tsai, Hsin-Hui Hu 2015-02-05T14:43:07Z 置信度 0.63
• A comparative analysis of the short-channel effects of double-gate, tri-gate and gate-all-around MOSFETs
  crossref Shankaranand Jha, Santosh Kumar Choudhary 2020-03-25T08:38:34Z 置信度 0.64
• A novel 2-D analytical model for the electrical characteristics of a gate-all-around heterojunction tunnel field-effect transistor including depletion regions
  crossref C. Usha, P. Vimala, T. S. Arun Samuel, M. Karthigai Pandian 2020-04-25T09:02:45Z 置信度 0.64
• The next generation of gate-all-around transistors
  crossref Lishu Wu 2023-07-26T17:40:21Z 置信度 0.64
• Gate-all-around structures for low-power applications
  crossref P. Prabhu Thapaswini 2025-12-17T03:23:51Z 置信度 0.66
• The Heterojunction Gate-All-Around Spintronic Tunnel FET (HG-Spin-TFET): A Pathway to Multifunctional, Ultra-Low-Power Nanoelectronics
  The relentless scaling of conventional CMOS technology is confronting a fundamental power wall, driven by the thermal limits of thermionic emission in MOSFETs. This paper addresses this challenge by proposing a novel device architecture: the Heterojunction Gat…
  crossref Ayush Verma 2025-08-04T01:38:59Z 置信度 0.82 materials sciencephysical sciencesneuromorphic engineeringoptoelectronicsquantum physics
• Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering
  crossref 2024-06-17T16:02:25Z 置信度 0.66
• Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length
  crossref Sanjay, B. Prasad, Anil Vohra 2020-11-02T14:03:08Z 置信度 0.64
• Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor
  In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage ( V on ) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first…
  crossref Seok Jung Kang, Jeong-Uk Park, Kyung Jin Rim, Yoon Kim 等 2020-01-22T04:51:54Z 置信度 0.79 remote sensingscience policyinterfaceexoplanetneuroscience
• All-solution-processed, flexible thin-film transistor based on PANI/PETA as gate/gate insulator
  An all-solution processed flexible thin-film transistor based on a PANI/PETA gate/gate insulator exhibited higher mobility than the device with a Si/SiO 2 gate/gate insulator because of large crystalline domains in the transition region.
  crossref Jin-Yong Hong, Dai Gun Yoon, Byung Doo Chin, Sung Hyun Kim 2015-12-09T11:12:45Z 置信度 0.76 optoelectronicscondensed matter physicstopological insulatormaterials sciencesemiconductor
• Ballistic Transport in n-type MoTe2 Junctionless Gate-All-Around Nanowire FETs: Temperature-Dependent Performance, CMOS Complementarity, and Benchmarking
  Ballistic-transport simulations of an n-type MoTe2 junctionless gate-all-around (JL-GAA) nanowire FET with 20 nm gate length and 2 nm HfO2 gate dielectric are reported. At 300 K the device achieves ION = 41.58 µA/µm, ION/IOFF = 2.87×10^10, and SSmin = 62.76 mV…
  crossref SANDIP Majumdar 2026-05-12T17:26:28Z 置信度 0.82 materials sciencephysical sciencescond-mat.mes-halloptoelectronicssemiconductor
• Design of Gate-All-Around TFET with Gate-On-Source for Enhanced Analog Performance
  crossref Navaneet Kumar Singh, Rajib Kar, Durbadal Mandal 2022-03-26T02:03:51Z 置信度 0.64
• Ge0.95Sn0.05 Gate-All-Around pChannel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub3 nm Nanowire Width
  crossref 2021-07-14T04:00:57Z 置信度 0.64
• Asymmetric Gate Stack Triple Metal Gate All Around MOSFET (AGSTM) for Improved Analog Applications
  crossref Arvind Ganesh, Jaskeerat Singh Mayall, Kshitij Goel, Sonam Rewari 2021-06-21T21:42:07Z 置信度 0.64
• Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study
  Abstract This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the chan…
  crossref Dariush Madadi, Saeed Mohammadi 2023-03-10T14:04:24Z 置信度 0.79 electrical engineering, electronic engineering, information engineeringsystems and controlcond-mat.mes-hallcontrol theoryphysics.app-ph
• Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications
  crossref Jaya Madan, R. S. Gupta, Rishu Chaujar 2016-10-04T21:21:22Z 置信度 0.63
• Physics based current and capacitance model of short-channel double gate and gate-all-around MOSFETs
  crossref H. Borli, S. Kolberg, T. A. Fjeldly 2010-12-08T09:27:32Z 置信度 0.61
• Design Optimization of InGaAs/GaAsSb-Based <i>P</i>-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor
  crossref Bo Gyeong Kim, Jae Hwa Seo, Young Jun Yoon, Min Su Cho 等 2019-04-26T04:54:46Z 置信度 0.64
• Vertically stacked gate-all-around arrays of SiGe nanowires
  crossref 2006-10-02T15:17:01Z 置信度 0.61
• Modeling and Simulation of Gate Engineered Gate All-Around MOSFET for Bio-Molecule Detection
  crossref B. Padmanaban, S. Sathiyamoorthy, R. Ramesh 2016-11-28T12:09:28Z 置信度 0.63
• Investigation of Gate-all-around p-type Dual Metal Double Gate Silicon Nanotube FET
  crossref A.Josephine Anucia, D. Gracia, D.Jackuline Moni 2022-05-30T19:10:00Z 置信度 0.64
• Challenges of Gate Stack TDDB in Gate-All-Around Nanosheet Towards Further Scaling
  crossref Huimei Zhou, Miaomiao Wang, Ernest Wu 2024-05-16T17:21:48Z 置信度 0.66
• 3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs
  crossref TaeYoon An, SoYoung Kim 2013-11-01T20:41:09Z 置信度 0.63
• Performance evaluation of dielectric modulation and metalloid T-shaped source/drain on gate-all-around junctionless transistor for improved analog/RF application
  crossref Yogesh Pratap, Sachin Kumar, R. S. Gupta, Mridula Gupta 2021-03-31T14:03:02Z 置信度 0.64
• Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap
  crossref Avtar Singh, Chandan Kumar Pandey 2021-01-28T12:44:47Z 置信度 0.64
• Random dopant fluctuation in gate-all-around nanowire FET
  crossref Cher Ming Tan, Xiangchen Chen 2016-04-28T20:18:49Z 置信度 0.63
• Correction: Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study
  crossref Dariush Madadi, Saeed Mohammadi 2024-02-12T09:03:29Z 置信度 0.66
• Corner effects in double-gate/gate-all-around MOSFETs
  crossref Hou Xiao-Yu, Zhou Fa-Long, Huang Ru, Zhang Xing 2007-02-27T09:14:48Z 置信度 0.61
• Dual Material Gate-Gate Stack-Elliptical Gate All Around (DMG-GS-EG) MOSFET – A Novel Device Concept for Improved Performance
  crossref Priyanka Pandey, Pooja Puri, Harsupreet Kaur 2018-10-04T18:41:22Z 置信度 0.63
• Precise analytical model for short channel Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET
  crossref Dheeraj Sharma, Santosh Kumar Vishvakarma 2012-11-16T04:37:40Z 置信度 0.63
• Lateral gate-all-around (GAA) poly-Si transistors
  crossref P. Kalavade, K.C. Saraswat 2002-11-13T15:00:11Z 置信度 0.61
• Precise Analytical Model for Short-Channel Quadruple-Gate Gate-All-Around MOSFET
  crossref Dheeraj Sharma, Santosh Kumar Vishvakarma 2013-03-08T19:43:15Z 置信度 0.63
• Noise Spectroscopy Analysis of Ion Behavior in Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors
  Abstract The transport and noise properties of fabricated, high‐performance, gate‐all‐around silicon liquid‐gated nanowire field‐effect transistor devices are investigated in different concentrations of MgCl 2 solutions. The critical concentration of MgCl 2 so…
  crossref Yongqiang Zhang, Nazarii Boichuk, Denys Pustovyi, Valeriia Chekubasheva 等 2023-09-23T00:36:48Z 置信度 0.79 quantum dotmaterials sciencephysics.app-phregolithcond-mat.mes-hall
• Performance Analysis of Sigma Delta ADC Developed using Electrically Doped GAPSb/InP Gate All Around Tunnel Field Effect Transistor
  crossref Amit Kumar Behera, Chithraja Rajan, Dip Prakash Samajdar, Anil Lodhi 等 2021-08-05T14:02:38Z 置信度 0.64
• Raised S/D gate-all-around CMOS using MILC
  crossref Chunshan Yin, P.C.H. Chan, V.W.C. Chan 2003-06-25T23:45:08Z 置信度 0.61
• Modeling of Quasi-Ballistic Silicon Cylindrical Gate-all-Around MOSFETs
  A compact model for the quasi-ballistic cylindrical gate-all-around MOSFET was developed by supplementing the ballistic framework previously disclosed by us with an original energy quantization model. The ballistic mobility is calculated for both degenerate an…
  crossref P. Vimala 2015-05-06T13:56:35Z 置信度 0.78 materials scienceplasma physicssemiconductorinternal medicineoptoelectronics
• Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor
  crossref Arvind Bisht, Yogendra Pratap Pundir, Pankaj Kumar Pal 2022-12-16T13:22:24Z 置信度 0.64
• Simulation-Based Analysis of AlGaN/GaN Gate All Around Field Effect Transistor (AlGaN/GaN GAA-FET)
  crossref Yogesh Kumar Verma, Varun Mishra, Rohit Gurjar, Rajeev Kumar Chauhan 等 2022-09-03T14:02:42Z 置信度 0.64
• A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
  Abstract This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplici…
  crossref Mu-Shih Yeh, Yung-Chun Wu, Kuan-Cheng Liu, Ming-Hsien Chung 等 2014-11-06T10:03:14Z 置信度 0.78 materials scienceneuromorphic engineeringoptoelectronicsgrapheneperovskite
• Impact of Light Excitation on Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors with Bowtie Antenna
  Abstract Recently it is shown that sensitivity of biosensors can be considerably improved using single trap phenomena resulting in two‐level random telegraph signal (RTS) switching in current. To develop the transistor structure with a predefined trap position…
  crossref Yongqiang Zhang, Kai Li, Nazarii Boichuk, Denys Pustovyi 等 2024-10-24T04:03:01Z 置信度 0.82 materials sciencequantum dotphysicsoptoelectronicsnanotechnology
• A Gate-All-Around Nanosheet Oxide Semiconductor Transistor by Selective Crystallization of InGaOx for Performance and Reliability Enhancement
  crossref Anlan Chen, Ki-woong Park, Kota Sakai, Sunbin Hwang 等 2025-07-18T17:42:20Z 置信度 0.66
• Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope
  crossref Faraz Najam, Sangsig Kim, Yun Seop Yu 2013-12-09T05:39:35Z 置信度 0.63
• Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)
  crossref Ajay, Rakhi Narang, Manoj Saxena, Mridula Gupta 2018-03-27T09:55:57Z 置信度 0.63
• Physics based model for potential distribution and threshold voltage of gate-all-around tunnel field effect transistor (GAA-TFET)
  crossref C. Usha, P. Vimala, V.N. Ramakrishnan 2020-12-18T05:52:04Z 置信度 0.64
• A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator
  Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient a…
  crossref Yannan Zhang, Ke Han, and Jiawei Li 2020-02-21T10:49:16Z 置信度 0.79 materials scienceoptoelectronicsnanotechnologysemiconductorcond-mat.mes-hall
• Role of Material Gate Engineering in Improving Gate All Around Junctionless (GAAJL) MOSFET Reliability Against Hot-Carrier Effects
  crossref H. Ferhati, F. Djeffal, T. Bentrcia 2021-01-28T21:48:50Z 置信度 0.64
• Performance Optimization of Cylindrical Gate-All-Around FETs Through Gate Workfunction Engineering
  crossref I. Venkatarameswar Reddy, J. Chinna Babu 2026-03-18T19:37:42Z 置信度 0.66
• Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET
  crossref Dheeraj Sharma, Santosh Kumar Vishvakarma 2015-06-26T17:54:57Z 置信度 0.63
• Transistor/gate level reliability modeling
  crossref Xu Liu 2019-09-10T22:58:40Z 置信度 0.64
• Development and Analysis of Gate Underlap GaN Gate-All-Around FETs
  crossref Sneha Singh, Priya Devi, Rudra Sankar Dhar 2025-06-11T11:39:42Z 置信度 0.66
• Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach
  crossref 2021-05-27T09:48:26Z 置信度 0.64
• Simulation of Different Structured Gate-All-Around FETs at 3 nm Node for Low-Power Integrated Circuits
  &lt;p&gt; This paper compares different types of GAA FET structures at 3 nm technology node using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. Single gate and gate stack structures are included in t…
  crossref Nathan Totorica, Wei Hu, Feng Li 2022-09-29T03:11:28Z 置信度 0.79 physics.app-phmulti-agent systemsai safetybatteryai governance
• A Review of the Gate-All-Around Nanosheet FET Process Opportunities
  In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall d…
  crossref Sagarika Mukesh, Jingyun Zhang 2022-11-04T03:28:10Z 置信度 0.79 networking and internet architecturesemiconductoremerging technologiesnanotechnologyinformation theory
• Simulation of Different Structured Gate-All-Around FETs at 3 nm Node for Low-Power Integrated Circuits
  This paper compares different types of GAA FET structures at 3 nm technology node using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. Single gate and gate stack structures are included in the analysi…
  crossref Nathan Totorica, Wei Hu, Feng Li 2022-09-28T23:11:27Z 置信度 0.79 physics.app-phmulti-agent systemsai safetybatteryai governance
• Performance Analysis and Characterization of Double Gate and Gate All Around MOSFET
  crossref Yusra Siddiqui, Nupur Mittal, Imran Ullah Khan 2022-01-18T22:20:07Z 置信度 0.64
• A High Sensitivity Novel Gas Sensor for Ethanol Sensing Using Gate Stack Junction-less Gate-All-Around (GS-JL-GAA) MOSFET for Industrial Application
  Abstract Gas sensors have gain attention with the technological advancement as they are widely used in industries, health care, agriculture and environmental monitoring. The MOSFET based sensor are the mostly preferred in the sensing application due to their r…
  crossref Abhinav Gupta, Akanksha Gupta, Rishabh Awasthi, Manish Rai 2025-12-01T06:09:09Z 置信度 0.82 materials scienceenvironmental sciencegreenhouse gascarbon dioxidewaste management
• Performance Analysis of Vertical Embedded Gate-Gate All Around FET with Quantum Confinement Effects
  crossref Amit Saini, Vishal Narula, Sangeeta Mangesh 2025-11-27T12:01:39Z 置信度 0.66
• Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET
  crossref Bhavya Kumar, Rishu Chaujar 2021-01-03T14:02:38Z 置信度 0.64
• A Gate-All-Around Floating-Gate Memory Device with Triangular-Shaped Poly-Si Nanowire Channels
  crossref K.H. Lee, H.C. Lin, T.Y. Huang 2015-09-18T05:43:25Z 置信度 0.63
• Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate
  Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of…
  crossref Yujie Ai, Ru Huang, Yiqun Wang, Jing Zhuge 等 2009-03-06T23:28:46Z 置信度 0.75 regolithmaterials scienceperovskitesoft roboticsbiochemical engineering
• Investigation of Gate-All-Around and Double-Gate InGaAs Negative-Capacitance FETs considering Quantum Capacitance
  crossref S.H. Lin, S.E. Huang, P. Su 2020-09-01T03:09:34Z 置信度 0.64
• Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method
  crossref Jiezhi Chen, Takura Saraya, Kousuke Miyaji, Ken Shimizu 等 2009-01-20T03:23:35Z 置信度 0.61
• TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance
  crossref Bhavya Kumar, Rishu Chaujar 2021-03-09T00:04:55Z 置信度 0.64
• DNA hydrogel to improve solution-gate graphene field effect transistor in all-solid-state
  Abstract The solution-gate graphene field effect transistor (Sg-GFET), as a popular sensing platform, its applications are still hindered by the deficiency in all-solid-state, due to the dependence on liquid-state gate-dielectric. Inspired by DNA hydrogel whic…
  crossref S. Hu, Y. Jia 2021-12-21T15:27:26Z 置信度 0.79 materials sciencenanotechnologyquantum dotgraphenephysics.app-ph
• Correction: All-solution-processed, flexible thin-film transistor based on PANI/PETA as gate/gate insulator
  Correction for ‘All-solution-processed, flexible thin-film transistor based on PANI/PETA as gate/gate insulator’ by Jin-Yong Hong et al. , RSC Adv. , 2015, 5 , 105785–105788.
  crossref Jin-Yong Hong, Kyoung-Hwan Shin, Dai Gun Yoon, Byung Doo Chin 等 2019-01-29T07:20:18Z 置信度 0.77 eess.asopticscs.irnatural language processingcontrol
• Scattering Parameter Analysis of Gate Stack Gate All Around (GS-GAA) FinFET at THz for RF Applications
  crossref Bhavya Kumar, Megha Sharma, Rishu Chaujar 2023-01-12T21:37:06Z 置信度 0.64
• Structure Effects in the gate-all-around Silicon Nanowire MOSFETs
  crossref Gengchiau Liang 2008-02-15T15:15:11Z 置信度 0.61
• Analysis of back gate and gate all around CNTFET structure
  crossref M. R. Tambekar, S. R. Nade, A. Gajarushi 2011-05-17T08:59:14Z 置信度 0.63
• Wrapping Carbon Nanotubes in a Gate-All-Around Geometry
  crossref A.D. Franklin 2015-09-18T05:43:25Z 置信度 0.63
• Electrothermal Model Parameters Extraction and Evaluation Based on BSIM-CMG for 7-nm Nanosheet Gate-All-Around Transistor
  crossref Ren-Hua Liu, Si-Qi Yang, Xiao-Jin Li, Ya-Bin Sun 等 2020-12-22T01:01:05Z 置信度 0.64
• The Low-Frequency Noise Behavior of Gate-All-Around Soi Transistors
  crossref E. Simoen, U. Magnusson, C. Claeys, J.P. Colinge 2005-08-24T16:50:14Z 置信度 0.61
• Challenges and future scope of gate-all-around (GAA) transistors
  crossref Shobhit Srivastava, Abhishek Acharya 2023-07-10T01:46:31Z 置信度 0.64
• Analysis of Single Event Transient Impact in Si/Si-Ge Gate-All-Around Nanowire Fet Using Tcad
  crossref Satheesh Kumar S, Rajakumar P S 2024-11-18T20:41:46Z 置信度 0.66
• Electrical performance of III-V gate-all-around nanowire transistors
  The performance of III-V inversion-mode and junctionless nanowire field-effect transistors are investigated using quantum simulations and are compared with those of silicon devices. We show that at ultrascaled dimensions silicon can offer better electrical per…
  crossref Pedram Razavi, Giorgos Fagas 2013-08-09T12:28:45Z 置信度 0.78 materials sciencecond-mat.mes-hallcond-mat.mtrl-scisemiconductoroptoelectronics
• Strain Effectiveness of Gate-all-around Silicon Nanowire n-MOSFET Transistors with Physical Analysis
  Abstract In this paper, we have discussed the effects of uniaxial tensile strain on the performance of gate-all-around (GAA) n-MOSFETs over the core cell SiGe structure are investigated for nanowire (NW) channel down to 5 nm to 10 nm. The strain has shown an i…
  crossref Amit Agarwal, Prashanta Chandra Pradhan, Bibhu Prasad Swain 2021-07-20T12:19:17Z 置信度 0.79 materials scienceoptoelectronicscond-mat.mes-hallsemiconductorphysical sciences
• High Frequency and Noise Model of Gate-All-Around MOSFETs
  crossref B. Nae, A. Lazaro, B. Iniguez 2009-03-19T19:22:54Z 置信度 0.61
• Gate induced drain leakage in nanowire gate all around field effect transistors and methods to reduce GIDL
  crossref Anhao Zhang 2023-11-15T13:00:15Z 置信度 0.64
• Numerical modeling on the optical characteristics of triple material gate stack gate all-around (TMGSGAA) MOSFET
  crossref R. Ramesh, M. Madheswaran, K. Kannan 2015-06-11T05:06:07Z 置信度 0.63
• Design and performance analysis of A Triple Material Double Gate Cylindrical Gate All Around (TMDG CGAA) MOSFET in Nano-meter Regime
  crossref Asmita Menaria, Rahul Pandey 2020-12-24T09:53:34Z 置信度 0.64
• Hot-carrier reliability on the optical characteristics of gate stack gate all-around (GSGAA) MOSFET considering quantum mechanical effects
  crossref M. Madheswaran, R. Ramesh, K. Kannan 2015-12-17T21:37:06Z 置信度 0.63
• Effect of Gate Bias on Graphene Channel of G⁴-FET and Gate-All-Around MOSFET
  crossref Md. Rakibul Alam, Hamidur Rahman 2019-03-01T03:03:24Z 置信度 0.64
• Quantization effects in gate-all-around nanowire MOSFETs: A numerical study
  crossref Salah Gamal, Dalia Selim 2010-06-29T11:56:35Z 置信度 0.61
• Gate Dielectric Engineering in p‐Type WSe ₂ Junctionless Gate‐All‐Around MOSFET
  Gate dielectric engineering is investigated in a p‐type WSe 2 junctionless gate‐all‐around (JL‐GAA) MOSFET (3 nm diameter, 2 nm oxide) using the FETtoy 2.0 simulator. Three high‐ κ dielectrics—Al 2 O 3 ( κ = 9), HfO 2 ( κ = 22), and ZrO 2 ( κ = 25)—are compare…
  crossref Sandip Majumdar 2026-08-14T04:44:48Z 置信度 0.82 materials sciencepharmacologyai governanceai safetyconsciousness
• Modeling of gate leakage in cylindrical gate-all-around transistors
  crossref Ravi Solanki, Saniya Minase, Ashutosh Mahajan, Rajendra Patrikar 2021-08-30T19:02:35Z 置信度 0.64
• TCAD Analysis and Modelling of Gate-Stack Gate All Around Junctionless Silicon NWFET Based Bio-Sensor for Biomedical Application
  crossref Mekonnen Getnet Yirak, Rishu Chaujar 2020-08-28T20:29:48Z 置信度 0.64
• Investigation of Dual-Material Double Gate Junctionless Accumulation-Mode Cylindrical Gate All Around (DMDG-JLAM-CGAA) MOSFET with High-k Gate Stack for low Power Digital Applications
  crossref Sumedha Gupta, Neeta Pandey, R S Gupta 2021-02-09T01:24:44Z 置信度 0.64
• Highly Efficient Gate Controllability of Rashba Spin-orbit Interaction in a Gate-all-around InAs Nanowire MOSFET
  crossref Keiko Takase, Guoqiang Zhang, Kouta Tateno, Satoshi Sasaki 2023-07-31T22:12:30Z 置信度 0.64
• (Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics
  This work reports a comprehensive evaluation of lateral gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, with both types of devices built with various doping schemes, and with GAA-NWFETs outperforming others per footprint. Optimized junctionle…
  crossref Anabela Veloso, Moon Ju Cho, Eddy Simoen, Geert Hellings 等 2016-05-20T09:56:42Z 置信度 0.78 reliabilitymaterials sciencecond-mat.mes-hallsystems and controlwearable computer
• Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET
  crossref Jaya Madan, Rishu Chaujar 2017-01-09T19:13:35Z 置信度 0.63
• Quantum Dot Gate Field-Effect Transistor: Device Structures
  crossref Supriya Karmakar 2013-11-20T10:17:51Z 置信度 0.63
• Impact of high‐<i>κ</i>gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor
  Abstract High‐ κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate…
  crossref Saeed Uz Zaman Khan, Md. Shafayat Hossain, Fahim Ur Rahman, Rifat Zaman 等 2014-09-08T06:42:57Z 置信度 0.78 materials scienceoptoelectronicscond-mat.mes-hallcond-mat.mtrl-sciphysical sciences
• Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier
  This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual…
  crossref Sarabdeep Singh, Leo Raj Solay, Sunny Anand, Naveen Kumar 等 2023-06-30T16:08:32Z 置信度 0.79 physics.app-phmaterials sciencecond-mat.mes-halloptoelectronicselectrical engineering, electronic engineering, information engineering
• (Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics
  Triple-gate finFET manufacturing implementation has been successfully enabling continuance of CMOS scaling and Moore’s law [1], but it faces increased scaling challenges for sub-10nm nodes. Gate-all-around (GAA) nanowire (NW) FETs with the thin-body of the dev…
  crossref Anabela Veloso, Moon Ju Cho, Eddy Simoen, Geert Hellings 等 2020-02-27T01:15:15Z 置信度 0.74
• Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation
  A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual s…
  crossref Jae-Min Sim, Bong-Seok Kim, In-Ho Nam, Yun-Heub Song 2021-07-30T12:59:24Z 置信度 0.79 materials scienceperovskitegrapheneneuromorphic engineeringquantum dot
• Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices
  crossref Huimei Zhou, Miaomiao Wang, Nicolas Loubet, Andrew Gaul 等 2023-05-15T17:50:57Z 置信度 0.64
• Analysis of screening effects in multiple-gate and gate-all-around Si NW array FETs
  crossref Ghader Darbandy, Sven Mothes, Michael SchrOter, Martin Claus 2017-11-02T17:11:00Z 置信度 0.63
• Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs
  crossref H. Borli, S. Kolberg, T.A. Fjeldly, B. Iniguez 2008-09-26T14:55:11Z 置信度 0.61
• Calretinin-expressing islet cells: a source of pre- and post-synaptic inhibition of non-peptidergic nociceptor input to the mouse spinal cord
  ABSTRACT Unmyelinated non-peptidergic nociceptors (NP afferents) arborise in lamina II of the spinal cord and receive GABAergic axoaxonic synapses, which mediate presynaptic inhibition. However, until now the source of this axoaxonic synaptic input was not kno…
  preprints 2023 置信度 0.80 biologyphysical medicine and rehabilitationpharmacologymedicineneuroscience
• Designed allosteric protein logic
  SUMMARY Regulation of the activity of proteins enables control of complex cellular processes. Allosteric regulation has been introduced individually into few natural proteins. Here, we present a generally applicable regulation of diverse proteins called INSRTR…
  preprints 2022 置信度 0.84 biologysynthetic biologycomputational biologyq-bio.bmgenetics