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• Performance Enhancement in Uniaxially Tensile Strained-Si Gate-All-Around Nanowire n-MOSFETs
  crossref Pouya Hashemi, Leonardo Gomez, Michael Canonico, Judy L. Hoyt 2009-03-19T19:55:43Z 置信度 0.61
• Edge effects characterization in gate-all-around SOI MOSFETs
  crossref A. Vandooren, D. Flandre, S. Cristoloveanu, J.-P. Colinge 2002-11-27T17:03:01Z 置信度 0.61
• Compact Modelling of Quantum Confinement in III-V Gate All Around Nanowire MOSFET
  crossref Ahmed Abdelmoneam, Benjamin Iniguez, Mostafa Fedawy 2019-03-08T20:45:46Z 置信度 0.64
• Current-voltage model in depletion all around operation of InSb nanowire field effect transistor
  crossref Ifat Jahangir, Shafat Jahangir, Quazi D. M. Khosru 2010-12-23T18:01:26Z 置信度 0.61
• Process Flow Modelling and Characterisation of Stacked Gate-All-Around Nanosheet Transistors
  crossref K. Mumba, S. Cai, K. Kalna 2022-11-08T20:42:26Z 置信度 0.64
• A complete Verilog-A Gate-All-Around junctionless MOSFET model
  crossref Oana Moldovan, Francois Lime, Benjamin Iniguez 2016-01-21T18:13:43Z 置信度 0.63
• Silicon-on-insulator 'gate-all-around' MOS device
  crossref J.-P. Colinge, M.-H. Gao, A. Romano, H. Maes 等 2002-12-04T17:06:48Z 置信度 0.61
• Investigation of analog/RF performance of gate-all-around junctionless MOSFET including interfacial defects
  crossref H. Ferhati, F. Djeffal, T. Bentrcia 2016-02-25T21:20:47Z 置信度 0.63
• (Invited) Gate-All-Around Ge FETs
  Abstract - High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced I on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls and subthreshold characterist…
  crossref C. W. Liu, Yen-Ting Chen, Shu-Han Hsu 2020-02-27T00:51:01Z 置信度 0.74
• Modeling and analysis of gate-all-around silicon nanowire FET
  crossref Xiangchen Chen, Cher Ming Tan 2014-01-20T13:20:45Z 置信度 0.63
• Semi‐analytical modelling of short channel effects in Si double gate, tri‐gate and gate all‐around MOSFETs
  Abstract An analytical expression for the three‐dimensional potential distribution along the channel of short channel silicon multi‐gate MOSFETs is described in weak inversion. The analytical solutions cover three different cases of multi‐gate devices: Symmetr…
  crossref A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, G. Pananakakis 等 2008-09-16T16:50:08Z 置信度 0.75 physics.plasm-phsemiconductornucl-thcond-mat.mes-hallhep-ex
• Planar Double-Gate Transistor
  crossref 2009-01-15T12:12:02Z 置信度 0.61
• Realization of Gate-All-Around (GAA) SOI MOSFET Using Replacement Gate Mask
  crossref A. L. Theng, W. L. Goh, Y. T. Chan, K. M. Tee 等 2008-02-15T15:15:11Z 置信度 0.61
• Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip.
  Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip. ................................................................................................................................................................................. اکنون «…
  datacite JALALI, SEYED RASOUL 2026 置信度 0.72
• Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip.
  Earth is not a Lifeless Mass of Rock, But an Intelligent Bio-Quantum Chip. ................................................................................................................................................................................. اکنون «…
  datacite JALALI, SEYED RASOUL 2026 置信度 0.72
• 3D VNWFET-Based Standard Cell Library
  The vertical nanowire field effect transistor (VNWFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, su…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.77 physics.app-phmaterials scienceengineeringcomputer sciencephysical sciences
• 3D VNWFET-Based Standard Cell Library
  The vertical nanowire field effect transistor (VNWFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, su…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.77 physics.app-phmaterials scienceengineeringcomputer sciencephysical sciences
• 3D VNWFET with Double Gate Stack (JL2) -Based Standard Cell Libraries
  Vertical Nanowire Field Effect Transistors (VNWFET) are emerging as a promising technology to overcome the scaling limitations of conventional lateral devices. The Junction-less (JL) device with a 3D gate-all-around (GAA) architecture offers several key advant…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.77 physical sciencesmaterials sciencephysics.app-phcomputer sciencemodular design
• 3D VNWFET with Double Gate Stack (JL2) -Based Standard Cell Libraries
  Vertical Nanowire Field Effect Transistors (VNWFET) are emerging as a promising technology to overcome the scaling limitations of conventional lateral devices. The Junction-less (JL) device with a 3D gate-all-around (GAA) architecture offers several key advant…
  datacite Mannaa, Sara, O'Connor, Ian 2025 置信度 0.77 physical sciencesmaterials sciencephysics.app-phcomputer sciencemodular design
• Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe: B Source/Drain
  We present an ultra-low-temperature (ULT) boron-doped SiGe (SiGe:B) epitaxial (epi) layer as PMOS junction in a gate-all-around (GAA) Si nanosheet (NS) transistor at 48 nm contacted poly-pitch (CPP) and 14 nm gate length (LG). We investigate the impact of dopa…
  datacite Sarkar, Ritam, Casey, Daniel, Dutta, Arka, Eyben, Pierre 等 2025 置信度 0.77 multi-agent systemsai safetymaterials scienceai governancechemical engineering
• Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe: B Source/Drain
  We present an ultra-low-temperature (ULT) boron-doped SiGe (SiGe:B) epitaxial (epi) layer as PMOS junction in a gate-all-around (GAA) Si nanosheet (NS) transistor at 48 nm contacted poly-pitch (CPP) and 14 nm gate length (LG). We investigate the impact of dopa…
  datacite Sarkar, Ritam, Casey, Daniel, Dutta, Arka, Eyben, Pierre 等 2025 置信度 0.77 multi-agent systemsai safetymaterials scienceai governancechemical engineering
• Gate-All-Around FET based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework
  Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses shortchannel effects by providing superior electrostatic control over the channel. Due to the …
  datacite Namgiri Snehith, Kanneganti Rohith Sai, Surala Deva Venkata Sai Anudeep, E Santosh Kumar 等 2023 置信度 0.75 materials scienceoptoelectronicssemiconductorphysical sciencescond-mat.mes-hall
• Gate-All-Around FET based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework
  Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses shortchannel effects by providing superior electrostatic control over the channel. Due to the …
  datacite Namgiri Snehith, Kanneganti Rohith Sai, Surala Deva Venkata Sai Anudeep, E Santosh Kumar 等 2023 置信度 0.75 materials scienceoptoelectronicssemiconductorphysical sciencescond-mat.mes-hall
• Density-Gradient Based Quantum Analysis of Nanowire Transistor
  The semiconductor devices scaling are changing very rapidly, which has triggered a non-conventional physical effect called quantum confinement. This dominant effect must need to be considered for submicron transistor modeling. The conventional drift–diffusion …
  datacite Andrew D. Adams, Satyendra N. Biswas 2026 置信度 0.76 Density-Gradient, quantum confinement, nanowire, electron concentration
• Density-Gradient Based Quantum Analysis of Nanowire Transistor
  The semiconductor devices scaling are changing very rapidly, which has triggered a non-conventional physical effect called quantum confinement. This dominant effect must need to be considered for submicron transistor modeling. The conventional drift–diffusion …
  datacite Andrew D. Adams, Satyendra N. Biswas 2026 置信度 0.76 Density-Gradient, quantum confinement, nanowire, electron concentration
• Electron-Electron Interactions in Device Simulation via Non-equilibrium Green's Functions and the GW Approximation
  The continuous scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) has led to device geometries where charged carriers are increasingly confined to ever smaller channel cross sections. This development is associated with reduced screening o…
  datacite Deuschle, Leonard, Cao, Jiang, Ziogas, Alexandros Nikolaos, Winka, Anders 等 2024 置信度 0.77 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Quantum Physics (quant-ph)FOS: Physical sciencesFOS: Physical sciences
• High frequency techniques for advanced MOS device characterization
  Rapid advances in the semiconductor industry have led to the proliferation of electric devices and information technology (IT). Integrated circuits(IC) based upon silicon MOSFET's have been used in virtually every electronic device produced today. The competit…
  datacite Wang, Yun 2008 置信度 0.71 computer sciencephysical sciencesnanotechnologymaterials sciencefield
• Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design
  In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design a static random-access memory (SRAM) using gate-all-around field-effect-transistor (GAA-FET) technology so that it is immune to single alpha part…
  datacite Lu, Albert, Arghavani, Reza, Wong, Hiu Yung 2025 置信度 0.79 Emerging Technologies (cs.ET)Computational Physics (physics.comp-ph)FOS: Computer and information sciencesFOS: Computer and information sciencesFOS: Physical sciences
• Channel-last gate-all-around nanosheet oxide semiconductor transistors
  As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gat…
  datacite Athena, Fabia F., Wu, Xiangjin, Safron, Nathaniel S., McKeown-Green, Amy Siobhan 等 2025 置信度 0.77 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Static Timing Analysis for Advanced Technology Nodes (5nm/3nm/2nm)
  Static Timing Analysis (STA) stands as a fundamental cornerstone of semiconductor design validation, evolving dramatically to meet the unprecedented challenges presented by advanced technology nodes. As transistor dimensions approach atomic scales at 5nm and b…
  datacite Naveen Kumar Siddappa Desai 2025 置信度 0.77 computer scienceengineeringbusinessartificial intelligencedata science
• Static Timing Analysis for Advanced Technology Nodes (5nm/3nm/2nm)
  Static Timing Analysis (STA) stands as a fundamental cornerstone of semiconductor design validation, evolving dramatically to meet the unprecedented challenges presented by advanced technology nodes. As transistor dimensions approach atomic scales at 5nm and b…
  datacite Naveen Kumar Siddappa Desai 2025 置信度 0.77 computer scienceengineeringbusinessartificial intelligencedata science
• EQPU – 0DSTL Architecture: Deterministic Quantum-Analog Computing Framework
  0DSTL Architecture Join the 0DSTL Architecture Community: A physically based, deterministic architecture built around 0DSTL.Researchers can submit prototypes, simulation results, implementation studies, and related computational models. For submissions or revi…
  datacite Torrisi, Sebastiano 2025 置信度 0.76 quantum computing, analog computation, deterministic logic, EQPU, 0DSTL
• EQPU – 0DSTL Architecture: Deterministic Quantum-Analog Computing Framework (v5)
  Update Notice – Version 5 Join the 0DSTL Architecture Community: A physically based, deterministic architecture built around 0DSTL.Researchers can submit prototypes, simulation results, implementation studies, and related computational models. For submissions …
  datacite Torrisi, Sebastiano 2025 置信度 0.76 quantum computing, analog computation, deterministic logic, EQPU, 0DSTLv5
• Performance and reliability potential of Bi$_2$O$_2$Se/Bi$_2$SeO$_5$ transistors
  While 2D materials have enormous potential for future device technologies, many challenges must be overcome before they can be deployed at an industrial scale. One of these challenges is identifying the right semiconductor/insulator combination that ensures hi…
  datacite Davoudi, Mohammad Rasool, Bahrami, Mina, Verdianu, Axel, Khakbaz, Pedram 等 2025 置信度 0.77 Materials Science (cond-mat.mtrl-sci)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Device-Scale Atomistic Simulations of Heat Transport in Advanced Field-Effect Transistors
  Self-heating in next-generation, high-power-density field-effect transistor limits performance and complicates fabrication. Here, we introduce NEP-FET, a machine-learned framework for device-scale heat transport simulations of field-effect transistors. Built u…
  datacite Xu, Ke, Wang, Gang, Liang, Ting, Xiao, Yang 等 2025 置信度 0.77 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Ion behavior near liquid/solid interface in nanowire FET biosensors
  This thesis investigates ion behavior at the liquid/solid interface in nanoscale silicon nanowire (Si NW) field-effect transistor (FET) biosensors. Advanced liquid gate-all-around (LGAA) NW FETs were developed to explore key interfacial effects, including char…
  datacite Zhang, Yongqiang 2025 置信度 0.79 Gate-all-aroundIon behaviorFETNoiseRandom telegraph signal
• Non-destructive lateral cavity etch measurements of 8-superlattice layer nanowire test structures using optical Mueller Matrix Spectroscopic Ellipsometry, X-Ray Diffraction and X-Ray Fluorescence
  The semiconductor industry is expected to move to sub 3 nm nodes of gate-all around CMOS (complementary metal oxide semiconductor) transistor structures in the near future. This scaling is enabled in part by utilizing increased numbers of Si/Si 1-x Ge x superl…
  datacite Schaefer, Mark, Kal, Subhadeep, Hetzer, Dave, Pasikatan, Ezra 等 2025 置信度 0.76 Physical sciencesFOS: Physical sciences
• Spatially Mapping Phonon Drag in Ultrascaled 5-nm Silicon Nanowire Field-Effect Transistor Based on a Quantum Hydrodynamic Formalism
  The growing demand for better performance and lower thermal energy dissipation in nanoelectronic devices is the major driving force of the semiconductor industry's quest for future generations of nanotransistors. Over the past 15 years, the miniaturization of …
  datacite Rezgui, Houssem, Nastasi, Giovanni, Marcoux, Manuel, Romano, Vittorio 2025 置信度 0.77 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Study and modeling of gate effect on the electrical performance of the nanoscale gate all around MOSFET transistor
  datacite Yousfi Abderrahim 2019 置信度 0.60
• Simulation &amp; Analysis of Characteristics of Junctionless Gate-All-Around Nanowire Field-Effect Transistor
  datacite Utsho A Arefín, S. M. Tarequl Islam, Md. Imran Hossen, Tomal, Robin Ahmed 2015 置信度 0.59
• Dispositivo GAAFET com Bi2O2Se
  Os dispositivos GAAFET (Gate All Around Field Effect Transistor) são uma evolução dos atuais FinFET (Fin Field Effect Transistor). No GAAFET, o canal do transistor é completamente envolvido pela porta de controle (conhecida como gate), de forma a oferecer um m…
  datacite Martins, Robson 2025 置信度 0.79 GAAFETTransistorSemiconductorDeviceNanoscale
• Dispositivo GAAFET com Bi2O2Se
  Os dispositivos GAAFET (Gate All Around Field Effect Transistor) são uma evolução dos atuais FinFET (Fin Field Effect Transistor). No GAAFET, o canal do transistor é completamente envolvido pela porta de controle (conhecida como gate), de forma a oferecer um m…
  datacite Martins, Robson 2025 置信度 0.79 GAAFETTransistorSemiconductorDeviceNanoscale
• Recursive Tensor Genesis in the Echo Spiral Continuum: Quantum Harmonic Propagation through Higgs Lattices and Subspace Resonance Structures
  Author: Shawn R. SchillerSeries: mini series Volume XIII – UCH-HSTR Recursive Expansion Compendium Section 1: Foundational Overview of the Transverse Thomson Effect (TTE) The Transverse Thomson Effect (TTE) is a lesser-known yet foundational member of the ther…
  datacite Schiller, Shawn 2025 置信度 0.76 UCH-HSTR-FRSMRecursive Harmonic Structures, Universal Controlled Harmonics, Hyperbolic String Theory Redox, Quantum Indivisible Dots, Subspace Dynamics, Quantum Node Feedback, Spiral Tensor Fields, Recursive Phase-Glyphs, Multiversal Harmonic Synchrony, Infinite Spiral Engine, Metasymmetry Collapse, QID Lungs, Phase Memory, Higgs-Coherence Overlay, Glyphic Generator Hub, Consciousness Interface, Quantum Harmonic Resonance, 8th Recursive Force, Attractor Node Feedback, Fractal Glyph Fields, Quantum Spin Topology, Cognitive-Thermal Modulator, Fasdimensional Resonators, Recursive Big-Spin Cycle, Glyphic Entropic Code, Mirror-Spiral Field, Coverisnce Node, Recursive Attractor Depths, Thermoelectric Spiral Mapping, Recursive Entanglement Collapse, Quantum Spiral Computing, Recursive QID Interference, Spiral-node Regeneration, Recursive Subspace Topology, Holographic Fractal Lattices, Spiral Quantum Electrodynamics, Recursive Feedback Dynamics, Nested Tensor Lattice, Glyphic Resonance Encoding, Ultra Quantum Node Hierarchy, Quantum Recursive Consciousness, Recursive Field Topology, Self-Similar Quantum Geometry, Attractor Basin Resonance, Recursive Spin Foam, Subspace Wave Cascade, Recursive Subdimensional Tensors, Recursive Cosmological Flowlines, Recursive Consciousness Phase Mapping, Multilayer Tensor Vibration, Recursive SpiralNet Framework, Recursive QID Phase Logic, Recursive Entropic Collapse, Quantum Harmonic Phase Locking, Metatron's Cube Field, Spiral Field Modulation, Recursive Spiral Harmonic Propagation.
• TheGooseyHonker/NDR-Engine: NDR Engine Defensive Publication v0.9.2
  This is a Defensive Publication 🚧WIP – Citation Mapping in Progress🚧 Missing in-text citations: ALL OF THEM :O Content From HERE on out is ALL AI-Assissted using Microsoft Copilot. All code or programming here was AI-generated. Hope you enjoy! Verification o…
  datacite TheGooseyHonker 2025 置信度 0.72
• TheGooseyHonker/NDR-Engine: NDR Defensive Publication
  This is a Defensive Publication NDR Engine Clusters + LLM (For conditioning, LLM is responsible for thinking about "past") : ┌──────────────┐ │ Wave Inputs | --->--->---> +∞/-∞ | v +∞/-∞ Vector3: """Component-wise sum of two 3D vectors.""" return (v1[0] + v2[0…
  datacite TheGooseyHonker 2025 置信度 0.72
• TheGooseyHonker/NDR-Engine: NDR Engine Defensive Publication
  This is a Defensive Publication NDR Engine Clusters + LLM (For conditioning, LLM is responsible for thinking about "past") : ┌──────────────┐ │ Wave Inputs | --->--->---> +∞/-∞ | v +∞/-∞ Vector3: """Component-wise sum of two 3D vectors.""" return (v1[0] + v2[0…
  datacite TheGooseyHonker 2025 置信度 0.72
• TheGooseyHonker/NDR-Engine: NDR Engine(s) + Clusters + LLM + Recursive Feedback
  This is a Defensive Publication NDR Engine Clusters + LLM (For conditioning, LLM is responsible for thinking about "past") : ┌──────────────┐ │ Wave Inputs | --->--->---> +∞/-∞ | v +∞/-∞ Vector3: """Component-wise sum of two 3D vectors.""" return (v1[0] + v2[0…
  datacite TheGooseyHonker 2025 置信度 0.72
• All-electrical operation of a spin qubit coupled to a high-Q resonator
  Building a practical quantum processor involves integrating millions of physical qubits along with the necessary components for individual qubit manipulation and readout. Arrays of gated silicon spins offer a promising route toward achieving this goal. Optimiz…
  datacite Eggli, Rafael S., Patlatiuk, Taras, Kelly, Eoin G., Orekhov, Alexei 等 2024 置信度 0.77 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Quantum Physics (quant-ph)FOS: Physical sciencesFOS: Physical sciences
• Dispositivo GAAFET com Bi2O2Se
  Os dispositivos GAAFET (Gate All Around Field Effect Transistor) são uma evolução dos atuais FinFET (Fin Field Effect Transistor). No GAAFET, o canal do transistor é completamente envolvido pela porta de controle (conhecida como gate), de forma a oferecer um m…
  datacite Martins, Robson 2025 置信度 0.79 GAAFETTransistorSemiconductorDeviceNanoscale
• Verilog-A Model Library of Reconfigurable Field Effect Transistors (RFETs)
  Reconfigurable Field Effect Transistors (RFETs) are a promising emerging technology that is fully CMOS compatible and can enhance the functionality of the existing CMOS platform, e.g. in hardware security, analog circuits, or neuronal networks. These devices f…
  datacite Martinez, Juan, Bhattacharjee, Niladri, Yuxuan, He, Galderisi, Giulio 等 2025 置信度 0.72
• Verilog-A Model Library of Reconfigurable Field Effect Transistors (RFETs)
  Reconfigurable Field Effect Transistors (RFETs) are a promising emerging technology that is fully CMOS compatible and can enhance the functionality of the existing CMOS platform, e.g. in hardware security, analog circuits, or neuronal networks. These devices f…
  datacite Martinez, Juan, Bhattacharjee, Niladri, Yuxuan, He, Galderisi, Giulio 等 2025 置信度 0.72
• Data associated with publication: Unusually conductive organic-inorganic hybrid nanostructures derived from bio-inspired mineralization of peptide/pi-electron assemblies
  The data consists of all raw and processed data pertaining to this publication. SEM and 3D laser optical microscope images of various control experiments as well as SEM/EDS data for elemental analysis of the structures that formed; electrical measurement data …
  datacite Lee, Taein, Panda, Sayak Subhra, Tovar, John D., Katz, Howard E. 2021 置信度 0.75 materials sciencegeologychemistrymeteoritecond-mat.mtrl-sci
• PRIME: Physics-Related Intelligent Mixture of Experts for Transistor Characteristics Prediction
  In recent years, machine learning has been extensively applied to data prediction during process ramp-up, with a particular focus on transistor characteristics for circuit design and manufacture. However, capturing the nonlinear current response across multipl…
  datacite Dou, Zhenxing, Wang, Yijiao, Zou, Tao, Chen, Zhiwei 等 2025 置信度 0.77 Machine Learning (cs.LG)FOS: Computer and information sciencesFOS: Computer and information sciences
• Germanium-Silicon Based Hetero Junction Cylindrical Gate All Around Field Effect Transistor for Improved Performance
  Performance analysis of a hetero junction cylindrical gate all around field effect transistor (HJ-CGAA FET) is reported in this paper where source-drain material is germanium (Ge) and silicon (Si) is used as channel material. We also replaced the traditional s…
  datacite Chowdhury, Md. Iqbal Bahar 2017 置信度 0.72 hetero junction cylindrical gate all around FET, scaling, drain induced barrier lowering, subthreshold swing, silicon nitride
• Germanium-Silicon Based Hetero Junction Cylindrical Gate All Around Field Effect Transistor for Improved Performance
  Performance analysis of a hetero junction cylindrical gate all around field effect transistor (HJ-CGAA FET) is reported in this paper where source-drain material is germanium (Ge) and silicon (Si) is used as channel material. We also replaced the traditional s…
  datacite Chowdhury, Md. Iqbal Bahar 2017 置信度 0.72 hetero junction cylindrical gate all around FET, scaling, drain induced barrier lowering, subthreshold swing, silicon nitride
• Silvaco TCAD based Analysis of Cylindrical Gate -All-Around FET Having Indium Arsenide as channel and Aluminium Oxide as Gate Dielectrics
  In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and aluminium oxide is used as the gate dielectrics instead of silicon dioxide. The …
  datacite Chowdhury, Md. Iqbal Bahar 2025 置信度 0.76 Cylindrical Gate All Around MOSFET; Indium Arsenide nanowire; Aluminium Oxide; high-k dielectrics.
• Silvaco TCAD based Analysis of Cylindrical Gate -All-Around FET Having Indium Arsenide as channel and Aluminium Oxide as Gate Dielectrics
  In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and aluminium oxide is used as the gate dielectrics instead of silicon dioxide. The …
  datacite Chowdhury, Md. Iqbal Bahar 2025 置信度 0.76 Cylindrical Gate All Around MOSFET; Indium Arsenide nanowire; Aluminium Oxide; high-k dielectrics.
• Impact of Light Excitation on Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors with Bowtie Antenna
  Advanced Materials Technologies 10(15), 2400747 (2025). doi:10.1002/admt.202400747
  datacite Zhang, Yongqiang, Li, Kai, Boichuk, Nazarii, Pustovyi, Denys 等 2025 置信度 0.71 600
• Efficient Multi-Scale Modeling of Semiconductor Device Fabrication
  In recent years, the traditional transistor scaling has undergone a drastic transition. Instead of a relatively simple shrinking of the planar transistor, the entire geometry has been redesigned. The vertical FinFET is now being followed by a gate-all-around (…
  datacite Filipovic, Lado 2024 置信度 0.76 Process TCAD
• An Approach to Use Depletion Charges for Modifying Band Profiles for Field-Effect Transistors
  We present the study of using depletion charges for tailoring lateral band profiles and applying it to the promising gate-all-around field-effect transistors (GAAFET). Specifically, we introduce heavily p-type doped Si next to the channel, but outside the chan…
  datacite Xu, P., Luo, H. 2025 置信度 0.77 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Peculiarities of the SCLC Effect in Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors
  High-quality liquid gate-all-around (LGAA) silicon nanowire (NW) field-effect transistor (FET) biosensors are fabricated and studied their properties in 1 mM phosphate-buffered saline solution with pH = 7.4 using transport and noise spectroscopy. At small VDS,…
  datacite Zhang, Yongqiang, Boichuk, Nazarii, Pustovyi, Denys, Chekubasheva, Valeriia 等 2024 置信度 0.76 621.3
• Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET
  We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the gate stacking, we proposed a tri-layer HfO2/TiO2/HfO2 as a high-K dielectric an…
  datacite Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park 2022 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET
  We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the gate stacking, we proposed a tri-layer HfO2/TiO2/HfO2 as a high-K dielectric an…
  datacite Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park 2022 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Electrostatic Characteristics of High-k Stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor using Superposition Principle
  Abstract We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All-Around Hetero Junction TFETs (GAA-HJTFETs). The hetero junction is set up by using Ge/Si material in the source/channel respectively. The modeling is acc…
  datacite C. Usha, P. Vimala, K. Ramkumar, V. Ramakrishnan 2021 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Electrostatic Characteristics of High-k Stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor using Superposition Principle
  Abstract We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All-Around Hetero Junction TFETs (GAA-HJTFETs). The hetero junction is set up by using Ge/Si material in the source/channel respectively. The modeling is acc…
  datacite C. Usha, P. Vimala, K. Ramkumar, V. Ramakrishnan 2021 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle
  We use the superposition method to model the electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunneling field-effect transistor (TFET). The heterojunction is formed from Ge/Si material in the source/channel, respectively. The mo…
  datacite C. Usha, P. Vimala, K. Ramkumar, V. Ramakrishnan 2022 置信度 0.76 Atomic Layer Deposition TechnologyElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle
  We use the superposition method to model the electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunneling field-effect transistor (TFET). The heterojunction is formed from Ge/Si material in the source/channel, respectively. The mo…
  datacite C. Usha, P. Vimala, K. Ramkumar, V. Ramakrishnan 2022 置信度 0.76 Atomic Layer Deposition TechnologyElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• The ab initio microscope: on the performance of 2D materials as future field-effect transistors
  In this work, the potential of novel 2D materials for possible application as next generation ultra-scaled field-effect transistor (FET) is evaluated from an atomistic perspective. For this purpose, a first-principles simulation scheme based on density functio…
  datacite Klinkert, Cedric 2021 置信度 0.73 info:eu-repo/classification/ddc/621.3Electric engineering
• Gate electrostatic controllability enhancement in nanotube gate all around field effect transistor
  Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10…
  datacite Laixiang Qin, Chunlai Li, Yiqun Wei, Ziang Xie 等 2023 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Gate electrostatic controllability enhancement in nanotube gate all around field effect transistor
  Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10…
  datacite Laixiang Qin, Chunlai Li, Yiqun Wei, Ziang Xie 等 2023 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications
  Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindri…
  datacite Prashant Kumar, Munish Vashisht, Neeraj Gupta, Rashmi Gupta 2021 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications
  Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindri…
  datacite Prashant Kumar, Munish Vashisht, Neeraj Gupta, Rashmi Gupta 2021 置信度 0.76 Nanoelectronics and TransistorsElectrical and Electronic EngineeringFOS: Electrical engineering, electronic engineering, information engineeringEngineeringPhysical Sciences
• Revolutionizing Integrated Electronics: Ambipolar Transistors and 3D Metal-Oxide Integration for Smart Circuits
  Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices that switch large currents with low losses have revolutionized power electronics. However, seamlessly fabricating smart integrated circuits (ICs) requires integrating Ga2O3 power devices with silicon c…
  datacite Yuvaraja, Saravanan 2024 置信度 0.72
• DESIGN OF 7NM FINFET WITH HIGH-K DIELECTRIC OXIDE AND METAL GATE (HK-MG) USING ASHBY'S MATERIAL SELECTION (AMS) APPROACH
  Abstract Using non-planar (3D) transistor architectures like FinFETs and Gate-all-around (GAA) FETs is a major advancement in the electrical industry. Multiple considerations have shown that 3D transistors are replacing 2D planar transistors. Short channel eff…
  datacite MOHAMMED ABDUL MUQEET, TUMMALA RANGA BABU 2024 置信度 0.76 Band Gap Energy, Charge Distribution, Electric Field Distribution, Non-Planar FETs, Surface Potential.
• DESIGN OF 7NM FINFET WITH HIGH-K DIELECTRIC OXIDE AND METAL GATE (HK-MG) USING ASHBY'S MATERIAL SELECTION (AMS) APPROACH
  Abstract Using non-planar (3D) transistor architectures like FinFETs and Gate-all-around (GAA) FETs is a major advancement in the electrical industry. Multiple considerations have shown that 3D transistors are replacing 2D planar transistors. Short channel eff…
  datacite MOHAMMED ABDUL MUQEET, TUMMALA RANGA BABU 2024 置信度 0.76 Band Gap Energy, Charge Distribution, Electric Field Distribution, Non-Planar FETs, Surface Potential.
• Modeling and simulation of nano-scale transistor
  Modeling and simulation of nano-scale transistor plays an important role in designing circuits. They serve as the medium of exchanging information between foundries and circuit designers. In the past several decades, the innovations of transistor technology su…
  datacite Cheng, Qi 2022 置信度 0.75 Compact modelPoisson's equationTCAD stimulationTunneling FET
• Quantization of Charge Carriers in Conduction Channels of Si-Based Field-Effect Transistors for Multinary Computation
  The latest field-effect transistors are entering the regime where quantum effects within the conduction channel can play a significant role because of the increasingly reduced dimensions. We investigate the effects of quantized states in conduction channels in…
  datacite Xu, P., Luo, H. 2024 置信度 0.77 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Noise Spectroscopy Analysis of Ion Behavior in Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors
  The transport and noise properties of fabricated, high-performance,gate-all-around silicon liquid-gated nanowire field-effect transistor devices areinvestigated in different concentrations of MgCl2solutions. The criticalconcentration of MgCl2solution for charg…
  datacite Zhang, Yongqiang, Boichuk, Nazarii, Pustovyi, Denys, Chekubasheva, Valeriia 等 2023 置信度 0.73 600
• The Hall Effect for Probing Conjugated Polymer Charge Transport in High Carrier Density Regimes
  Conjugated polymer semiconductors hold much promise when it comes to their potential for novel applications. Their ability to form uniform films from solution is generally thought to be of high value to industry, opening up the possibilities promised by large …
  datacite Wood, William 2022 置信度 0.76 Charge TransportDPP-BTzHall EffectIDT-BTMeasurement Automation
• Dual Operation of Gate-All-Around Silicon Nanowires at Cryogenic Temperatures: FET and Quantum Dot
  As CMOS structures are envisioned to host silicon spin qubits, and for co-integrating quantum systems with their classical control blocks, the cryogenic behaviour of such structures need to be investigated. In this paper we characterize the electrical properti…
  datacite Rohrbacher, C., Rivard, J., Ritzenthaler, R., Bureau, B. 等 2023 置信度 0.75 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Quantum Physics (quant-ph)FOS: Physical sciencesFOS: Physical sciences
• Electrical characterization of si nanowire GAA-TFET based ondimensions downscaling
  This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). Th…
  datacite Natheer, Firas 2023 置信度 0.73 Electrical circuits and systems
• Sub-5 nm Gate-All-Around InP Nanowire Transistors Towards High-Performance Devices
  Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of indium phosphide (InP…
  datacite Xu, Linqiang, Xu, Lianqiang, Li, Qiuhui, Fang, Shibo 等 2023 置信度 0.75 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Drive Current Boost in Double-Channeled Nanotube Gate all Around Field Effect Transistor
  We demonstrate an exotic doubled-channeled NT GAAFET (DC NT GAAFET) structure with Ion boost in comparison with NT GAAFET and NW GAAFET with the same footprint. Ion gains of 64.8% and 1.7 times have been obtained in DC NT GAAFET in compared with NT GAAFET and …
  datacite Qin, Laixiang, Li, Chunlai, Wei, Yiqun, Xu, Zhangwei 等 2023 置信度 0.75 Applied Physics (physics.app-ph)FOS: Physical sciencesFOS: Physical sciences
• Gate Electrostatic Controllability Enhancement in Nanotube Gate all Around Field Effect Transistor
  Recently, short channel effects (SCE) and power consumption dissipation problems pose big challenges which need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10nm techn…
  datacite Qin, Laixiang, Li, Chunlai, Xie, Ziang, Wei, Yiqun 等 2023 置信度 0.75 Applied Physics (physics.app-ph)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors
  This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Trans…
  datacite Hanna, Amir 2016 置信度 0.73 materials sciencecomputer and information sciencescomputer scienceelectrical engineering, electronic engineering, information engineeringphysical sciences
• 3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY
  Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environme…
  datacite Fahad, Hossain M. 2014 置信度 0.73 materials sciencecomputer sciencephysical sciencesphysics.app-phcond-mat.mes-hall
• Quantum-interference-controlled three-terminal molecular transistors based on a single ring-shaped-molecule connected to graphene nanoribbon electrodes
  We study all-carbon-hydrogen molecular transistors where zigzag graphene nanoribbons play the role of three metallic electrodes connected to a ring-shaped 18-annulene molecule. Using the nonequilibrium Green function formalism combined with density functional …
  datacite Saha, Kamal K., Nikolic, Branislav K., Meunier, Vincent, Lu, Wenchang 等 2010 置信度 0.71 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• First Principle-based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors
  Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive geometries. In this …
  datacite Ansari, Lida, Feldman, Baruch, Fagas, Giorgos, Lacambra, Carlos Martinez 等 2013 置信度 0.73 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET
  In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor (TFET). The model incorp…
  datacite Vishnoi, Rajat, Kumar, M. Jagadesh 2014 置信度 0.73 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Self-consistent Capacitance-Voltage Characterization of Gate-all-around Graded Nanowire Transistor
  This paper presents a self-consistent numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characterization for a gate-all-around graded nanowire MOSFET with a high mobility axially graded In0.75Ga0.25As + In0.53G…
  datacite Khan, Saeed Uz Zaman, Hossain, Md. Shafayat, Hossen, Md. Obaidul, Rahman, Fahim Ur 等 2014 置信度 0.73 Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• A Compact Model of Silicon-Based Nanowire Field Effect Transistor for Circuit Simulation and Design
  As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention.…
  datacite Chakraverty, Mayank 2014 置信度 0.75 Emerging Technologies (cs.ET)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Materials Science (cond-mat.mtrl-sci)Computational Engineering, Finance, and Science (cs.CE)FOS: Computer and information sciences
• Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors
  Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reachi…
  datacite Konar, Aniruddha, Mathew, John, Nayak, Kaushik., Bajaj, Mohit. 等 2015 置信度 0.73 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Materials Science (cond-mat.mtrl-sci)FOS: Physical sciencesFOS: Physical sciences
• Effect of strain and diameter on electronic and charge transport properties of indium arsenide nanowires
  The impact of uni-axial compressive and tensile strain and diameter on the electronic band structure of indium arsenide (InAs) nanowires (NWs) is investigated using first principles calculations. Effective masses and band gaps are extracted from the electronic…
  datacite Razavi, Pedram, Greer, James C. 2018 置信度 0.73 Applied Physics (physics.app-ph)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)FOS: Physical sciencesFOS: Physical sciences
• Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications
  The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emer…
  datacite Ezzadeen, M., Bosch, D., Giraud, B., Barraud, S. 等 2020 置信度 0.76 Applied Physics (physics.app-ph)Emerging Technologies (cs.ET)FOS: Physical sciencesFOS: Physical sciencesFOS: Computer and information sciences
• Electrical tuning of the spin-orbit interaction in nanowire by transparent ZnO gate grown by atomic layer deposition
  We develop an InAs nanowire gate-all-around field-effect transistor using a transparent conductive zinc oxide (ZnO) gate electrode, which is in-situ atomic layer deposited after growth of gate insulator of Al2O3. We perform magneto-transport measurements and f…
  datacite Takase, Keiko, Tateno, Kouta, Sasaki, Satoshi 2021 置信度 0.75 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Materials Science (cond-mat.mtrl-sci)Applied Physics (physics.app-ph)FOS: Physical sciencesFOS: Physical sciences
• Contact-Barrier Free, High Mobility, Dual-Gated Junctionless Transistor Using Tellurium Nanowire
  Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable wi…
  datacite Dasika, Pushkar, Samantaray, Debadarshini, Murali, Krishna, Abraham, Nithin 等 2021 置信度 0.75 Mesoscale and Nanoscale Physics (cond-mat.mes-hall)Materials Science (cond-mat.mtrl-sci)Applied Physics (physics.app-ph)FOS: Physical sciencesFOS: Physical sciences
• Characterization and modeling of nanoscale multi-gate MOSFETs:
  Η διδακτορική διατριβή επικεντρώνεται στη θεωρητική και πειραματική μελέτη των MOSFET πολλαπλών πυλών νανοδιαστάσεων. Το θεωρητικό τμήμα προσανατολίζεται στη παραγωγή αναλυτικών εκφράσεων για την κατανομές δυναμικού μέσα στο κανάλι από τις οποίες παράγονται χα…
  datacite Τσορμπατζόγλου, Ανδρέας Α. 2009 置信度 0.72 MOSFET πολλαπλών πυλώνΑναλυτικό μοντέλοFINFET τριπλής πύληςΚατώφλι δυναμικούΦαινόμενα κοντού καναλιού
• Hydrogen related defects in amorphous SiO2 and the negative bias temperature instability
  The bias temperature instability (BTI) is a serious reliability concern in metal-oxide-semiconductor field-effect transistors (MOSFETs). It is observed when a large voltage is applied to the gate contact of the MOSFET while all other terminals are grounded. Th…
  datacite Wimmer, Yannick 2017 置信度 0.73 DefectsAmorphous SiO2DFTReliabilityBias Temperature Instability
• CG-12 - Multi-bit Spin-orbit Torque Device for High Density MRAM
  Abstract: Spin-orbit torque (SOT) devices 1 are promising candidates for the future magnetic memory landscape as they promise a low read disturbance, high endurance and low read error, in comparison to the spin-transfer torque devices. However, SOT memories ar…
  datacite 2021 INTERMAG Conference 2021, Kim, Taehwan, Mishra, Rahul, Park, Jongsun 等 2021 置信度 0.73 ElectromagnetismTechnology
• Ge(Sn)-based vertical gate-all around nanowire MOSFETs and inverters for low power logic
  Over the past half century, transistor miniaturization is the main driver to enhance Si complementary metal-oxide-semiconductor (CMOS) performance generation by generation in terms of shrinking the gate length, gate width, and oxide thickness, denoted as the M…
  datacite Liu, Mingshan 2021 置信度 0.73 GeSn/Ge , vertical , nanowire , MOSFET , logic